Semiconductor device

A semiconductor device, comprising:

• a transistor;
• a first device;
• a back side insulating structure disposed below the transistor and the first device;
• a front side conductive structure disposed on the transistor and the first device;
• a passivation structure disposed between the first device and the back side insulating structure;
• a back side conductive pattern disposed between the back side insulating structure and the transistor;
• and
• a back side interconnection structure in the back side insulating structure, the back side interconnection structure being electrically connected with the back side conductive pattern,
• wherein the transistor includes:
• a first source/drain pattern and a second source/drain pattern;
• a plurality of active layers disposed between the first source/drain pattern and the second source/drain pattern, the plurality of active layers being arranged in a vertical direction;
• a gate electrode surrounding each active layer of the plurality of active layers;
• and
• a gate dielectric layer between the gate electrode and the plurality of active layers, and
• wherein the first device includes:
• a semiconductor body including a first semiconductor region and a second semiconductor region, the first semiconductor region having a first conductivity type, and the second semiconductor region having a second conductivity type and being configured to form a PN junction with the first semiconductor region;
• a first semiconductor pattern disposed on the first semiconductor region of the semiconductor body, the first semiconductor pattern having the first conductivity type, and an impurity concentration of the first semiconductor pattern being higher than an impurity concentration of the first semiconductor region;
• and
• a second semiconductor pattern disposed on the second semiconductor region of the semiconductor body, the second semiconductor pattern having the second conductivity type, and an impurity concentration of the second semiconductor pattern being higher than an impurity concentration of the second semiconductor region,
• wherein at least a portion of the first semiconductor pattern or at least a portion of the second semiconductor pattern is disposed at the same level as a portion of the first source/drain pattern or a portion of the second source/drain pattern,
• wherein a lower surface of the semiconductor body is disposed at a level lower than a center between an upper surface and a lower surface of the back side conductive pattern,
• wherein the passivation structure includes a high-κ dielectric layer, a dielectric constant of the high-κ dielectric layer being higher than a dielectric constant of silicon oxide, and
• wherein the first conductivity type is a P-type and the second conductivity type is an N-type, or the first conductivity type is the N-type and the second conductivity type is the P-type.

A semiconductor device, comprising:

• a lower base;
• and
• a semiconductor chip disposed on the lower base and electrically connected with the lower base,
• wherein the semiconductor chip includes:
• a transistor;
• a first device;
• a back side insulating structure disposed below the transistor and the first device;
• a front side conductive structure disposed on the transistor and the first device;
• a passivation structure disposed between the first device and the back side insulating structure;
• a back side conductive pattern disposed between the back side insulating structure and the transistor;
• and
• a back side interconnection structure in the back side insulating structure, the back side interconnection structure electrically connected with the back side conductive pattern,
• wherein the transistor includes:
• a first source/drain pattern and a second source/drain pattern;
• a plurality of active layers disposed between the first source/drain pattern and the second source/drain pattern, the plurality of active layers being arranged in a vertical direction;
• a gate electrode surrounding each active layer of the plurality of active layers;
• and
• a gate dielectric layer between the gate electrode and the plurality of active layers, and
• wherein the first device includes:
• a semiconductor body including a first semiconductor region and a second semiconductor region, the first semiconductor region having a first conductivity type, and the second semiconductor region having a second conductivity type and being configured to form a PN junction with the first semiconductor region;
• a first semiconductor pattern disposed on the first semiconductor region of the semiconductor body, the first semiconductor pattern having the first conductivity type, and an impurity concentration of the first semiconductor pattern being higher than an impurity concentration of the first semiconductor region;
• and
• a second semiconductor pattern disposed on the second semiconductor region of the semiconductor body, the second semiconductor pattern having the second conductivity type, and an impurity concentration of the second semiconductor pattern being higher than an impurity concentration of the second semiconductor region, and
• wherein the first conductivity type is a P-type and the second conductivity type is an N-type, or the first conductivity type is the N-type and the second conductivity type is the P-type, and
• wherein the passivation structure is disposed outside an area between the back side insulating structure and the transistor.