Data transfer in port switch memory
AssigneeLodestar Licensing Group LLC
InventorFrank F. Ross
Life of this patent
Estimating the term…
Abstract
The present disclosure includes apparatuses and methods related to data transfer in memory. An example apparatus can include a first number of memory devices coupled to a host via a first number of ports and a second number of memory devices coupled to the first number of memory device via a second number of ports, wherein a first number of commands are executed to transfer data between the first number of memory devices and the host via the first number of ports and a second number of commands are executed to transfer data between the first number of memory device and the second number of memory device via the second number of ports.
Claims20
A system comprising:
- a host device;
- and
- a dual in-line memory module (DIMM) comprising a controller and a dynamic random access memory (DRAM) device, and wherein the controller is configured to:
- provide a ready signal to the host device, wherein the ready signal indicates a readiness of the controller to execute a command;
- receive the command from the host device at the controller after providing the ready signal;
- and
- access, based on the command, the DRAM device.
A method comprising:
- providing a ready signal to a host device, wherein the host device is configured to couple to a dual in-line memory module (DIMM);
- receiving a command from the host device at a controller of the DIMM after providing the ready signal;
- and
- accessing, based on the command, a dynamic random access memory (DRAM) device of the DIMM.
A device, comprising
- a plurality of buses configured to couple to a host device, wherein the plurality of buses comprises a subset of the plurality of buses and a bus separate from the subset of the plurality of buses;
- a plurality of dynamic random access memory (DRAM) devices configured to couple to the host device via the subset of the plurality of buses;
- and
- a controller configured to couple to the plurality of DRAM devices and to couple, via the bus, to the host device, wherein the controller is configured to:
- provide a ready signal to the host device while not busy;
- receive a command from the host device at a controller after providing the ready signal;
- and
- perform, based on the command, a read or write operation on a DRAM device of the plurality of DRAM devices.
Dependencies are inferred from the claim text.