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US 2026/0147040 A1Published application
Hardware decoder for run-length encoded mask bits for in-system automatic test pattern generation (atpg)
AssigneeQUALCOMM Incorporated
InventorsSrinivas PATIL, Rajesh Kumar TIWARI, Nir MAOR
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Abstract
A computer implemented decoding method includes decoding a number of run-length encoded mask strings to obtain decoded mask bits for each of a number of scan channels. The method also includes applying the decoded mask bits to automatic test pattern generator (ATPG) scan response data of each scan channel to obtain a multiple input signature register (MISR) signature.
Claims20
A computer implemented decoding method, comprising:
- decoding a plurality of run-length encoded mask strings to obtain decoded mask bits for each scan channel of a plurality of scan channels;
- and
- applying the decoded mask bits to automatic test pattern generator (ATPG) scan response data of each scan channel to obtain a multiple input signature register (MISR) signature.
A decoding apparatus, comprising:
- a plurality of finite state machines, each configured to decode a plurality of run-length encoded mask strings to obtain decoded mask bits for each scan channel of a plurality of scan channels;
- and
- a plurality of logical AND gates configured to apply the decoded mask bits to automatic test pattern generator (ATPG) scan response data of each scan channel to obtain a multiple input signature register (MISR) signature.
An apparatus, comprising:
- at least one memory;
- and
- at least one processor coupled to the at least one memory, the at least one processor configured:
- to decode a plurality of run-length encoded mask strings to obtain decoded mask bits for each scan channel of a plurality of scan channels;
- and
- to apply the decoded mask bits to automatic test pattern generator (ATPG) scan response data of each scan channel to obtain a multiple input signature register (MISR) signature.
3 more elements
Dependencies are inferred from the claim text.