Multi-loop frequency translator with reduced area/power

A system comprising:

• a transmitter coupled to receive a first data packet, said line card to re-time said first data packet with reference to a re-timing clock, and to transmit a first re-timed packet;
• and
• a multi-loop frequency translator (MLFT) to generate an output clock based on one or more clock sources, said MLFT comprising:
• a plurality of loops containing a primary loop and a plurality of secondary loops according to a hierarchy,
• wherein each loop of said plurality of loops is characterized by a corresponding specification frequency at which the loop is to ideally operate at,
• wherein said primary loop is highest in said hierarchy and each of the secondary loops is completed by components of loops higher in said hierarchy,
• wherein each loop at a lower level provides a corresponding correction signal to correct any drift from the specification frequency of a respective loop at one or more of the loops at higher levels,
• wherein said primary loop is an open-loop circuit.