Address range identification

A method comprising:

• storing a plurality of entries, each of the plurality of entries identifying a corresponding contiguous range of addresses spanning one or more of a plurality of addressable regions of an address space, wherein content stored at each of the plurality of addressable regions is individually retrievable by fetch circuitry from a memory hierarchy, wherein each of the plurality of entries is suitable to be used for generation of one or more speculative memory access requests for retrieval of the content stored at the corresponding contiguous range of addresses in response to a trigger condition being satisfied;
• storing information indicative of a candidate new entry identifying a contiguous range of addresses spanning one or more of the plurality of addressable regions;
• in response to receiving an indication of a memory access request specifying an addressable region of the plurality of addressable regions, the addressable region being other than one of the plurality of addressable regions which is both contiguous with and subsequent to the one or more of the plurality of addressable regions spanned by the contiguous range of addresses, performing a determination of whether the addressable region is within a predefined range of the contiguous range of addresses;
• and
• in response to the addressable region being within the predefined range of the contiguous range of addresses, modifying the contiguous range of addresses to include the addressable region.

A non-transitory computer-readable medium storing computer-readable code, which when executed by one or more computers, generates a semiconductor design for fabrication of an apparatus comprising:

• storage circuitry configured to store a plurality of entries, each of the plurality of entries identifying a corresponding contiguous range of addresses spanning one or more of a plurality of addressable regions of an address space, wherein content stored at each of the plurality of addressable regions is individually retrievable by fetch circuitry from a memory hierarchy, and wherein each of the plurality of entries is suitable to be used for generation of one or more speculative memory access requests for retrieval of the content stored at the corresponding contiguous range of addresses in response to a trigger condition being satisfied;
• and
• control circuitry configured:
• to store information indicative of a candidate new entry identifying a contiguous range of addresses spanning one or more of the plurality of addressable regions;
• in response to receipt of an indication of a memory access request specifying an addressable region of the plurality of addressable regions, the addressable region being other than one of the plurality of addressable regions which is both contiguous with and subsequent to the one or more of the plurality of addressable regions spanned by the contiguous range of addresses, to perform a determination of whether the addressable region is within a predefined range of the contiguous range of addresses;
• and
• in response to the addressable region being within the predefined range of the contiguous range of addresses, to modify the contiguous range of addresses to include the addressable region.