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US 2026/0136674 A1Published application

Semiconductor device and display device

AssigneeSemiconductor Energy Laboratory Co., Ltd.

InventorsHajime KIMURA, Atsushi UMEZAKI

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Abstract Drawings Claims Description

Abstract

A semiconductor device including a circuit which does not easily deteriorate is provided. The semiconductor device includes a first transistor, a second transistor, a first switch, a second switch, and a third switch. A first terminal of the first transistor is connected to a first wiring. A second terminal of the first transistor is connected to a second wiring. A gate and a first terminal of the second transistor are connected to the first wiring. A second terminal of the second transistor is connected to a gate of the first transistor. The first switch is connected between the second wiring and a third wiring. The second switch is connected between the second wiring and the third wiring. The third switch is connected between the gate of the first transistor and the third wiring.

Claims25

Dependent claims

Claim 1(canceled) · 1 wordNo dependents Claim 2A semiconductor device · 283 words2 dependent Claim 3A semiconductor device · 283 words2 dependent Claim 4A semiconductor device · 299 words2 dependent Claim 5A semiconductor device · 309 words2 dependent Claim 6A semiconductor device · 318 words2 dependent Claim 7A semiconductor device · 328 words2 dependent Claim 8A semiconductor device · 334 words2 dependent Claim 9A semiconductor device · 344 words2 dependent

(canceled)

A semiconductor device comprising a gate driver;

wherein the gate driver comprises first to fifth transistors,
wherein one of a source and a drain of the first transistor is electrically connected to a first clock signal line,
wherein the other of the source and the drain of the first transistor is electrically connected to a second gate signal line,
wherein one of a source and a drain of the second transistor is electrically connected to a power supply line,
wherein the other of the source and the drain of the second transistor is electrically connected to the second gate signal line,
wherein one of a source and a drain of the third transistor is electrically connected to a first gate signal line,
wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the first transistor,
wherein a gate of the third transistor is electrically connected to the second clock signal line,
wherein one of a source and a drain of the fourth transistor is electrically connected to the power supply line,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor,
wherein a gate of the fourth transistor is electrically connected to the gate of the second transistor,
wherein one of a source and a drain of the fifth transistor is electrically connected to the second clock signal line,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the gate of the second transistor, and
wherein a gate of the fifth transistor is electrically connected to the gate of the first transistor.

11 more elements

A semiconductor device comprising a gate driver;

wherein the gate driver comprises first to fifth transistors,
wherein one of a source and a drain of the first transistor is electrically connected to a first clock signal line,
wherein the other of the source and the drain of the first transistor is electrically connected to a second gate signal line,
wherein one of a source and a drain of the second transistor is electrically connected to a power supply line,
wherein the other of the source and the drain of the second transistor is electrically connected to the second gate signal line,
wherein one of a source and a drain of the third transistor is electrically connected to a first gate signal line,
wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the first transistor,
wherein a gate of the third transistor is electrically connected to the second clock signal line,
wherein one of a source and a drain of the fourth transistor is electrically connected to the power supply line,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor,
wherein a gate of the fourth transistor is electrically connected to the gate of the second transistor,
wherein one of a source and a drain of the fifth transistor is electrically connected to the second clock signal line,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the gate of the second transistor, and
wherein a gate of the fifth transistor is electrically connected to the gate of the first transistor.

11 more elements

A semiconductor device comprising a gate driver;

wherein the gate driver comprises first to fifth transistors,
wherein one of a source and a drain of the first transistor is electrically connected to a first clock signal line,
wherein the other of the source and the drain of the first transistor is electrically connected to a second gate signal line,
wherein one of a source and a drain of the second transistor is electrically connected to a power supply line,
wherein the other of the source and the drain of the second transistor is electrically connected to the second gate signal line,
wherein one of a source and a drain of the third transistor is electrically connected to a first gate signal line,
wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the first transistor,
wherein a gate of the third transistor is electrically connected to the second clock signal line,
wherein one of a source and a drain of the fourth transistor is electrically connected to the power supply line,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor,
wherein a gate of the fourth transistor is electrically connected to the gate of the second transistor,
wherein one of a source and a drain of the fifth transistor is electrically connected to the second clock signal line,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the gate of the second transistor,
wherein a gate of the fifth transistor is electrically connected to the gate of the first transistor, and
wherein a channel width of the second transistor is larger than that of the fifth transistor.

12 more elements

A semiconductor device comprising a gate driver;

wherein the gate driver comprises first to fifth transistors,
wherein the first to fifth transistors have the same polarity,
wherein one of a source and a drain of the first transistor is electrically connected to a first clock signal line,
wherein the other of the source and the drain of the first transistor is electrically connected to a second gate signal line,
wherein one of a source and a drain of the second transistor is electrically connected to a power supply line,
wherein the other of the source and the drain of the second transistor is electrically connected to the second gate signal line,
wherein one of a source and a drain of the third transistor is electrically connected to a first gate signal line,
wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the first transistor,
wherein a gate of the third transistor is electrically connected to the second clock signal line,
wherein one of a source and a drain of the fourth transistor is electrically connected to the power supply line,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor,
wherein a gate of the fourth transistor is electrically connected to the gate of the second transistor,
wherein one of a source and a drain of the fifth transistor is electrically connected to the second clock signal line,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the gate of the second transistor,
wherein a gate of the fifth transistor is electrically connected to the gate of the first transistor, and
wherein a channel width of the second transistor is larger than that of the fifth transistor.

13 more elements

A semiconductor device comprising a gate driver;

wherein the gate driver comprises first to fifth transistors and a capacitor,
wherein one of a source and a drain of the first transistor is electrically connected to a first clock signal line,
wherein the other of the source and the drain of the first transistor is electrically connected to a second gate signal line,
wherein one of a source and a drain of the second transistor is electrically connected to a power supply line,
wherein the other of the source and the drain of the second transistor is electrically connected to the second gate signal line,
wherein one of a source and a drain of the third transistor is electrically connected to a first gate signal line,
wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the first transistor,
wherein a gate of the third transistor is electrically connected to the second clock signal line,
wherein one of a source and a drain of the fourth transistor is electrically connected to the power supply line,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor,
wherein a gate of the fourth transistor is electrically connected to the gate of the second transistor,
wherein one of a source and a drain of the fifth transistor is electrically connected to the second clock signal line,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the gate of the second transistor,
wherein a gate of the fifth transistor is electrically connected to the gate of the first transistor,
wherein one electrode of the capacitor is electrically connected to the gate of the first transistor, and
wherein the other electrode of the capacitor is electrically connected to the second gate signal line.

13 more elements

A semiconductor device comprising a gate driver;

wherein the gate driver comprises first to fifth transistors and a capacitor,
wherein the first to fifth transistors have the same polarity,
wherein one of a source and a drain of the first transistor is electrically connected to a first clock signal line,
wherein the other of the source and the drain of the first transistor is electrically connected to a second gate signal line,
wherein one of a source and a drain of the second transistor is electrically connected to a power supply line,
wherein the other of the source and the drain of the second transistor is electrically connected to the second gate signal line,
wherein one of a source and a drain of the third transistor is electrically connected to a first gate signal line,
wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the first transistor,
wherein a gate of the third transistor is electrically connected to the second clock signal line,
wherein one of a source and a drain of the fourth transistor is electrically connected to the power supply line,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor,
wherein a gate of the fourth transistor is electrically connected to the gate of the second transistor,
wherein one of a source and a drain of the fifth transistor is electrically connected to the second clock signal line,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the gate of the second transistor,
wherein a gate of the fifth transistor is electrically connected to the gate of the first transistor,
wherein one electrode of the capacitor is electrically connected to the gate of the first transistor, and
wherein the other electrode of the capacitor is electrically connected to the second gate signal line.

14 more elements

A semiconductor device comprising a gate driver;

wherein the gate driver comprises first to fifth transistors and a capacitor,
wherein one of a source and a drain of the first transistor is electrically connected to a first clock signal line,
wherein the other of the source and the drain of the first transistor is electrically connected to a second gate signal line,
wherein one of a source and a drain of the second transistor is electrically connected to a power supply line,
wherein the other of the source and the drain of the second transistor is electrically connected to the second gate signal line,
wherein one of a source and a drain of the third transistor is electrically connected to a first gate signal line,
wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the first transistor,
wherein a gate of the third transistor is electrically connected to the second clock signal line,
wherein one of a source and a drain of the fourth transistor is electrically connected to the power supply line,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor,
wherein a gate of the fourth transistor is electrically connected to the gate of the second transistor,
wherein one of a source and a drain of the fifth transistor is electrically connected to the second clock signal line,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the gate of the second transistor,
wherein a gate of the fifth transistor is electrically connected to the gate of the first transistor,
wherein one electrode of the capacitor is electrically connected to the gate of the first transistor,
wherein the other electrode of the capacitor is electrically connected to the second gate signal line, and
wherein a channel width of the second transistor is larger than that of the fifth transistor.

14 more elements

A semiconductor device comprising a gate driver;

wherein the gate driver comprises first to fifth transistors and a capacitor,
wherein the first to fifth transistors have the same polarity,
wherein one of a source and a drain of the first transistor is electrically connected to a first clock signal line,
wherein the other of the source and the drain of the first transistor is electrically connected to a second gate signal line,
wherein one of a source and a drain of the second transistor is electrically connected to a power supply line,
wherein the other of the source and the drain of the second transistor is electrically connected to the second gate signal line,
wherein one of a source and a drain of the third transistor is electrically connected to a first gate signal line,
wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the first transistor,
wherein a gate of the third transistor is electrically connected to the second clock signal line,
wherein one of a source and a drain of the fourth transistor is electrically connected to the power supply line,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor,
wherein a gate of the fourth transistor is electrically connected to the gate of the second transistor,
wherein one of a source and a drain of the fifth transistor is electrically connected to the second clock signal line,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the gate of the second transistor,
wherein a gate of the fifth transistor is electrically connected to the gate of the first transistor,
wherein one electrode of the capacitor is electrically connected to the gate of the first transistor,
wherein the other electrode of the capacitor is electrically connected to the second gate signal line, and
wherein a channel width of the second transistor is larger than that of the fifth transistor.

15 more elements

Dependencies are inferred from the claim text.

Facts

Application: 19/430,482Filed 23 Dec 2025
Priority: JP 2009-20909910 Sep 2009
Published: 14 May 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification32 codes

H10D 86/60
Characterised by multiple TFTs: wherein the TFTs are in active matrices
G02F 1/13306
Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements: circuit arrangements or driving methods for the control of…
G02F 1/1339
Constructional arrangements; Manufacturing methods: gaskets; Spacers; Sealing of cells
G02F 1/136213
Active matrix addressed cells: storage capacitors associated with the pixel electrode

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