Memory device
AssigneesSamsung Electronics Co., Ltd., Iucf-Hyu (Industry-University Cooperation Foundation Hanyang University)
InventorsMin Tae RYU, Byong-Deok CHOI, Sungwon YOO, Wonsok LEE, Yongsang YOO
Life of this patent
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Abstract
A memory device includes a first oxide semiconductor layer, a first source/drain layer connected to the first oxide semiconductor layer in a first direction, a first bitline extending in a second direction and connected to the first oxide semiconductor layer, a first electrode located on the first source/drain layer and connected to the first source/drain layer, a second electrode forming a first capacitor with the first electrode, and a second bitline extending in the second direction and connected to the second electrode.
Claims20
A memory device, comprising:
- a first oxide semiconductor layer;
- a first source/drain layer connected to the first oxide semiconductor layer in a first direction;
- a first bitline extending in a second direction and connected to the first oxide semiconductor layer;
- a first electrode located on the first source/drain layer and connected to the first source/drain layer;
- a second electrode forming a first capacitor with the first electrode;
- and
- a second bitline extending in the second direction and connected to the second electrode.
A memory device comprising:
- a first bitline extending in a first direction;
- a second bitline extending in the first direction and spatially separated from the first bitline;
- a first oxide semiconductor layer connected to a first region of the first bitline in a second direction perpendicular to the first direction;
- a first source/drain layer connected to the first oxide semiconductor layer in the second direction and positioned to face the second bitline in a third direction perpendicular to both the first direction and the second direction;
- and
- a first capacitor coupled between the first source/drain layer and the second bitline.
Dependencies are inferred from the claim text.