Level shifter

A level shifter for converting an input signal between a first supply voltage and a ground voltage into an output signal between a second supply voltage and the ground voltage, and the second supply voltage is greater than the first supply voltage, and the level shifter comprising:

• a first P-type transistor, wherein a source terminal of the first P-type transistor receives the second supply voltage, a drain terminal of the first P-type transistor is coupled to a first node, and a gate terminal of the first P-type transistor is coupled to a second node, wherein a voltage at the second node is used as the output signal;
• a second P-type transistor, wherein a source terminal of the second P-type transistor receives the second supply voltage, a drain terminal of the second P-type transistor is coupled to the second node, and a gate terminal of the second P-type transistor is coupled to the first node;
• a first N-type transistor, wherein a source terminal of the first N-type transistor receives the ground voltage, a drain terminal of the first N-type transistor is coupled to a third node, and a gate terminal of the first N-type transistor receives the input signal;
• a second N-type transistor, wherein a source terminal of the second N-type transistor receives the ground voltage, a drain terminal of the second N-type transistor is coupled to a fourth node, and a gate terminal of the second N-type transistor receives an inverted input signal, wherein the input signal and the inverted input signal are complementary to each other;
• a third N-type transistor, wherein a source terminal of the third N-type transistor is coupled to the third node, a drain terminal of the third N-type transistor is coupled to the first node, and a gate terminal of the third N-type transistor receives the input signal;
• a fourth N-type transistor, wherein a source terminal of the fourth N-type transistor is coupled to the fourth node, a drain terminal of the fourth N-type transistor is coupled to the second node, and a gate terminal of the fourth N-type transistor receives the inverted input signal;
• and
• a pulling device connected to the second node, wherein the pulling device receives an enable signal,
• wherein when at least one of the first supply voltage and the second supply voltage is not provided and the enable signal is not activated, the pulling device is turned on and the output signal is maintained at a specified logic level, wherein when the first supply voltage and the second supply voltage are both provided, the enable signal is activated, the pulling device is turned off and the output signal changes with a change of the input signal.