Memory circuits with sense amplifiers selectively coupled to access lines and methods for operating the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsTung-Cheng Chang, Ku-Feng Lin
Life of this patent
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Abstract
A memory circuit includes a first memory cell configured to store a first data bit; a second memory configured to store a second data bit; a sense amplifier coupled to the first memory cell and the second memory cell through a data bit line and a reference bit line, respectively; a first switch; and a second switch. The first switch is selectively coupled between the data bit line and a first input node of the sense amplifier, and the second switch is selectively coupled between the reference bit line and a second input node of the sense amplifier.
Claims20
A memory circuit, comprising:
- a first memory cell configured to store a first data bit;
- a second memory cell configured to store a second data bit;
- a sense amplifier coupled to the first memory cell and the second memory cell through a data bit line and a reference bit line, respectively;
- a first switch;
- and
- a second switch;
- wherein the first switch is selectively coupled between the data bit line and a first input node of the sense amplifier, and the second switch is selectively coupled between the reference bit line and a second input node of the sense amplifier.
A memory circuit, comprising:
- a sense amplifier configured to identify a data bit stored by a first memory cell, based on comparing a first signal present on a data bit line connecting the first memory cell to the sense amplifier and a second signal present on a reference bit line connecting a second memory cell to the sense amplifier;
- a first switch configured to selectively couple the data bit line to a first input node of the sense amplifier based on an enable signal;
- and
- a second switch configured to selectively couple the reference bit line to a second input node of the sense amplifier based on the enable signal.
A method for operating a memory circuit, comprising:
- pre-charging a data bit line and a reference bit line to a first logic state, with the data bit line and the reference bit line coupled to a first input node and a second input node of a sense amplifier, respectively, wherein the data bit line is coupled to a data cell while the reference bit line is coupled to a reference cell;
- discharging the data bit line and the reference bit line, with the first input node and the second input node remaining coupled to the data bit line and the reference bit line, respectively, and with the first input node and the second input node each decoupled from any transistor;
- and
- latching a data bit stored by the data cell, with the first input node and the second input node decoupled from the data bit line and from the reference bit line, respectively.
Dependencies are inferred from the claim text.