Performance monitoring unit workload sampling with minimal system interferences

A system comprising:

• at least one processor;
• a PMU configured to monitor the at least one processor;
• a sampling controller configured to receive data from the PMU and comprising a plurality of control registers;
• an uncacheable memory path leading from the sampling controller to one or more memory subsystems;
• and
• instructions stored in the sampling controller, the instructions being executable to:
• initiate, in response to detecting a start event associated with the at least one processor and defined by a first control register of the plurality of control registers, a PMU to generate event data for processor events defined by a second control register of the plurality of control registers and according to a control filtering exception level dictated by a third control register of the plurality of control registers;
• detect that a sampling event frequency dictated by the first control register of the plurality of control registers has been reached;
• trigger the PMU to release a PMU data trace comprising the generated event data;
• store the PMU data trace on an uncacheable buffer at a buffer address dictated by a fourth control register of the plurality of control registers;
• and
• move, in response to detecting a stop event associated with the at least one processor, the PMU data trace from the uncacheable buffer along an uncacheable memory path to a memory subsystem.

A method for sampling PMU workloads with minimal system interferences comprising:

• initiating, by a sampling controller comprising a plurality of control registers, a PMU to generate event data for processor core events defined by a first control register of the plurality of control registers and according to a control filtering exception level dictated by a second control register of the plurality of control registers;
• detecting, by the sampling controller, that a sampling event frequency dictated by a third control register of the plurality of control registers has been reached;
• storing, by the sampling controller, a PMU data trace released by the PMU and comprising the generated event data on an uncacheable buffer;
• and
• moving, by the sampling controller, the PMU data trace along an uncacheable memory path to a memory subsystem in response to the PMU becoming disabled.