US 2026/0128736 A1Published application

Clock glitch detection circuit and method thereof

AssigneePUFsecurity Corporation

InventorsCHI-YI SHAO, SHENG-TSUNG WANG, CHIH-NI WU

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Abstract

The present application discloses a clock glitch detection circuit including a clock generator, a counter, and a detection unit. The clock generator receives an input clock signal, and generates a reference clock signal having a frequency higher than that of the input clock signal when the input clock signal is at a first voltage. The counter counts a current accumulated number of cycles of the reference clock signal that occur while the input clock signal is at the first voltage. The detection unit calculates a difference between the previous and the current accumulated numbers after the input clock signal changes from the first voltage to a second voltage. The detection unit generates an alarm signal according to the difference between the previous and the current accumulated numbers and stores the current accumulated number as the previous accumulated number.

Claims23

Dependent claims

A clock glitch detection circuit comprising:

a first clock generator configured to receive an input clock signal, and generate a first reference clock signal when the input clock signal is at a first voltage, wherein a frequency of the first reference clock signal is higher than a frequency of the input clock signal;
a first counter configured to count a first current accumulated number of cycles of the first reference clock signal that occur while the input clock signal is at the first voltage in a counting phase;
and
a first detection unit configured to calculate a difference between a first previous accumulated number and the first current accumulated number after the input clock signal changes from the first voltage to a second voltage in a judging phase later than the counting phase, and, after the difference between the first previous accumulated number and the first current accumulated number is calculated, store the first current accumulated number as the first previous accumulated number and generate a first alarm signal according to the difference between the first previous accumulated number and the first current accumulated number.

1 more element

A method for detecting clock glitches of an input clock signal with a clock glitch detection circuit, wherein the clock glitch detection circuit comprises a first clock generator, a first counter, and a first detection unit, and the method comprises:

generating, by the first clock generator, a first reference clock signal when the input clock signal is at a first voltage, wherein a frequency of the first reference clock signal is higher than a frequency of the input clock signal;
counting, by the first counter, a first current accumulated number of cycles of the first reference clock signal;
calculating, by the first detection unit, a difference between a first previous accumulated number and the first current accumulated number after the input clock signal changes from the first voltage to a second voltage;
generating, by the first detection unit, a first alarm signal according to the difference between the first previous accumulated number and the first current accumulated number after the difference between a first previous accumulated number and the first current accumulated number is calculated;
and
storing, by the first detection unit, the first current accumulated number as the first previous accumulated number after the difference is calculated.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 19/373,729Filed 30 Oct 2025
Priority: 4 Nov 2024
Published: 7 May 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

G11C 29/44
Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details: indication or identification of errors, e.g. for…
G01R 31/31727
Testing of digital circuits: clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing…
G06F 1/08
Generating or distributing clock signals or signals derived directly therefrom: clock generators with changeable or programmable clock frequency
G06F 21/75
To assure secure computing or processing of information: by inhibiting the analysis of circuitry or operation

Family

Application63/715,647Us provisional application · filed 4 Nov 2024
US 2026/0128736 A1This patent

From the US filing history. Foreign family members aren’t listed.

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