US 2026/0128114 A1 · MEMORY DEVICE WITH BUILT-IN SELF-TEST

Abstract

The present application discloses a memory device. The memory device includes a one-time programmable (OTP) cell array, a physical unclonable function (PUF) cell array, and a controller. The OTP cell array includes a plurality of OTP cells. The PUF cell array includes a plurality of PUF cells. The controller performs a first read operation upon the PUF cell array to read a plurality of first bit values, performs a second read operation upon the PUF cell array to read a plurality of second bit values after the first read operation, performs a comparison operation upon the first bit values and the second bit values, and determines whether to allow an OTP load operation for reading the OTP cell array according to a result of the comparison operation.

Claims21

Dependent claims

A memory device comprising:

a one-time programmable (OTP) cell array comprising a plurality of OTP cells;
a physical unclonable function (PUF) cell array comprising a plurality of PUF cells;
and
a controller configured to perform a first read operation upon the PUF cell array to read a plurality of first bit values, perform a second read operation upon the PUF cell array to read a plurality of second bit values after the first read operation, perform a comparison operation upon the plurality of first bit values and the plurality of second bit values, and determine whether to allow an OTP load operation for reading the OTP cell array at least according to a result of the comparison operation.

1 more element

A method for confirming stability of a memory device, wherein the memory device comprises an one-time programmable (OTP) cell array, and a physical unclonable function (PUF) cell array, the OTP cell array comprises a plurality of OTP cells, the PUF cell array comprises a plurality of PUF cells, and the method comprises:

performing a first read operation upon the PUF cell array to read a plurality of first bit values;
performing a second read operation upon the PUF cell array to read a plurality of second bit values after the first read operation;
performing a comparison operation upon the plurality of first bit values and the plurality of second bit values;
and
determining whether to allow an OTP load operation for reading the OTP cell array at least according to a result of the comparison operation.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

19/378,048Filed 3 Nov 2025

Priority

4 Nov 2024

Published

7 May 2026

Term ends

Not estimatedThe source records don’t support an estimate.

Classification13 codes

G11C 29/44
Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details: indication or identification of errors, e.g. for…
G01R 31/31727
Testing of digital circuits: clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing…
G06F 1/08
Generating or distributing clock signals or signals derived directly therefrom: clock generators with changeable or programmable clock frequency
G06F 21/75
To assure secure computing or processing of information: by inhibiting the analysis of circuitry or operation

Memory device with built-in self-test

Life of this patent

Memory device with built-in self-test

Life of this patent

Abstract

Claims21