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US 2026/0128072 A1Published application
Systems and methods for scan chain interface for non-volatile storage bits
AssigneeEverspin Technologies, Inc.
InventorsSyed M. ALAM, Jacob T. WILLIAMS
Life of this patent
Estimating the term…
Abstract
A scan chain circuitry for a memory device includes a first non-volatile storage bit (nvbit) configured to receive a shared control signal, a second nvbit configured to receive the shared control signal, a first flip-flop connected to the first nvbit, and a second flip-flop connected to the second nvbit and the first flip-flop. The first flip-flop enables loading a first data in (din) to the first nvbit based on a clock signal, and the second flip-flop enables loading a second din to the second nvbit based on the clock signal.
Claims20
A bitcell for a memory device, comprising:
- a left leg, the left leg comprising:
- one or more first magnetic tunnel junctions (MTJs);
- one or more first write circuitries connected to the one or more first MTJs, the one or more first write circuitries configurable to execute a write operation for the one or more first MTJs based on a write control signal;
- and
- one or more first read circuitries connected to the one or more first MTJs, the one or more first read circuitries configurable to execute a read operation for the one or more first MTJs based on a read control signal;
- and
- a right leg, the right leg comprising:
- one or more second magnetic tunnel junctions (MTJs);
- one or more second write circuitries connected to the one or more second MTJs, the one or more second write circuitries configurable to execute a write operation for the one or more second MTJs based on the write control signal;
- and
- one or more second read circuitries connected to the one or more second MTJs, the one or more second read circuitries configurable to execute a read operation for the one or more second MTJs based on the read control signal.
8 more elements
A bitcell for a memory device, comprising:
- a first leg including:
- one or more first magnetoresistive devices;
- one or more first write circuitries connected to the one or more first magnetoresistive devices, the one or more first write circuitries configurable to execute a write operation for the one or more first magnetoresistive devices based on a write control signal and a first clock signal;
- and
- one or more first read circuitries connected to the one or more first magnetoresistive devices, the one or more first read circuitries configurable to execute a read operation for the one or more first magnetoresistive devices based on a read control signal and a second clock signal;
- and
- a second leg including:
- one or more second magnetoresistive devices;
- one or more second write circuitries connected to the one or more second magnetoresistive devices, the one or more second write circuitries configurable to execute a write operation for the one or more second magnetoresistive devices based on the write control signal and the first clock signal;
- and
- one or more second read circuitries connected to the one or more second magnetoresistive devices, the one or more second read circuitries configurable to execute a read operation for the one or more second magnetoresistive devices based on the read control signal and the second clock signal.
8 more elements
A bitcell for a memory device, comprising:
- a first leg including:
- one or more first magnetic tunnel junctions (MTJs);
- one or more first write circuitries connected to the one or more first MTJs, the one or more first write circuitries configurable to execute a write operation for the one or more first MTJs and optionally configurable to be grounded;
- and
- one or more first read circuitries connected to the one or more first MTJs, the one or more first read circuitries configurable to execute a read operation for the one or more first MTJs based at least on a first clock signal;
- and
- a second leg including:
- one or more second magnetic tunnel junctions (MTJs);
- one or more second write circuitries connected to the one or more second MTJs, the one or more second write circuitries configurable to execute a write operation for the one or more second MTJs and optionally configurable to be grounded;
- and
- one or more second read circuitries connected to the one or more second MTJs, the one or more second read circuitries configurable to execute a read operation for the one or more second MTJs based at least on a second clock signal.
8 more elements
Dependencies are inferred from the claim text.