Loading patent…
OwnerNguyet-Phuong TRAN, Philippe RODRIGUEZ +2inventors
InventorsNguyet-Phuong TRAN, Philippe RODRIGUEZ, Frédéric MILESI, Laurent BRUNET
Estimating the term…
A method for manufacturing semiconductor devices integrating PMOS and NMOS transistors is provided. The method begins by depositing a layer of silicon-germanium alloy SiGe onto a semiconductor-on-insulator substrate including a silicon layer on a buried oxide layer, which itself is located on a semiconductor support. An isolation trench is then created, separating the regions intended for the NMOS and PMOS transistors. The PMOS region is masked to allow a strain to be applied in the silicon layer of the NMOS region, via a STRASS recrystallization technique. Then, the NMOS region is masked and the mask of the PMOS region is removed in order to apply a strain by germanium enrichment.
A method (P1, P2) for manufacturing a semiconductor device (D1) comprising at least one PMOS transistor and at least one NMOS transistor, said method comprising the following steps of:
A semiconductor device (D1) comprising a PMOS transistor and an NMOS transistor separated from each other by a dielectric isolation trench (STI), the NMOS transistor being produced in a crystalline silicon layer disposed on a buried oxide layer (BOX), the lattices of the crystalline silicon layer experiencing internal mechanical tensile strains, the PMOS transistor being produced in a crystalline layer of Si(1-x)Gex disposed on a buried oxide layer (BOX), the lattices of the crystalline layer of Si(1-x)Gex experiencing internal mechanical compression strains.
Dependencies are inferred from the claim text.