Acceleration device, heterogeneous computing architecture, and data processing method

An acceleration device, comprising:

• a storage assembly;
• at least one local optical port, wherein each of the at least one local optical port is connected to each remote optical port, and the remote optical port is an optical port on another acceleration device;
• an external routing assembly connected to each local optical port, configured to receive a data frame to be processed transmitted by the at least one local optical port and/or an internal routing assembly, in response to the data frame to be processed satisfying an outward forwarding condition, output a data frame to be output obtained based on the data frame to be processed to a corresponding local optical port, and in response to the data frame to be processed satisfying an inward writing condition, output the data frame to be processed to the internal routing assembly;
• the internal routing assembly, configured to write data to be computed in the data frame to be processed into the storage assembly and generate a first trigger instruction, in response to receiving a forwarding instruction, read result data corresponding to the forwarding instruction from the storage assembly, and transmit the data frame to be processed obtained based on the result data to the external routing assembly;
• and
• a computing assembly, configured to compute the data to be computed in the storage assembly based on a target trigger instruction, write the result data into the storage assembly after obtaining the result data, and generate the forwarding instruction, wherein the target trigger instruction is the first trigger instruction or a second trigger instruction generated by a host based on a current computing task.