Low-latency determination of optimal low-power modes (lpms) of inactive circuits in an integrated circuit (ic) and related power management methods

Abstract

Some logic circuits in an IC may have periods of inactivity, such as when the functions they provide are not needed, but they continue to consume power. In an exemplary IC, a power manager determines that a logic circuit is in an inactive state, employs a lookup table circuit to determine an optimal low-power mode (LPM) for the logic circuit based on an anticipated duration of the inactive state, and causes the circuit to enter the optimal LPM. Determining an optimal LPM from a lookup table circuit minimizes the latency of the LPM determination. Determining an optimal LPM may include comparing net energy consumptions of LPMs with different rates of power consumption. In some examples, the power manager provides at least one of a circuit identifier, a circuit frequency, and a memory interface frequency to the lookup table circuit and receives the optimal LPM.

Dependencies are inferred from the claim text.