Inter-segment swapping method for controlling of segmented digital-to-analog converter

An inter-segment swapping (ISS) method for controlling a plurality of segments of a segmented digital-to-analog converter (DAC), comprising:

• receiving a first output code derived from higher significant bits of a digital input code of the segmented DAC;
• receiving one or more second output codes derived from lower significant bits of the digital input code of the segmented DAC;
• deriving a first pre-ISS control code of a higher-significant-bit segment included in the plurality of segments of the segmented DAC from the first output code, wherein the first pre-ISS control code comprises first control bits corresponding to first DAC cells of the higher-significant-bit segment, respectively;
• deriving one or more second pre-ISS control codes of one or more lower-significant-bit segments included in the plurality of segments of the segmented DAC from the one or more second output codes, wherein the one or more second pre-ISS control codes comprise second control bits corresponding to second DAC cells of the one or more lower-significant-bit segments, respectively;
• and
• performing an ISS operation upon the first pre-ISS control code and the one or more second pre-ISS control codes to generate a first post-ISS control code of the higher-significant-bit segment and one or more second post-ISS control codes of the one or more lower-significant-bit segments, comprising:
• swapping a first control bit of a first DAC cell included in the higher-significant-bit segment for second control bits of all second DAC cells included in the one or more lower-significant-bit segments;
• or
• swapping second control bits of all second DAC cells included in the one or r lower-significant-bit segments for a first control bit of a first DAC cell included in the higher-significant-bit segment.

A segmented digital-to-analog converter (DAC) comprising:

• a plurality of segments, comprising:
• a higher-significant-bit segment, having first DAC cells;
• and
• a lower-significant-bit segment, having second DAC cells;
• a combining circuit, configured to combine a plurality of analog outputs of the plurality of segments;
• a segmentation circuit, configured to derive a first output code from higher significant bits of a digital input code of the segmented DAC, and derive a second output code from lower significant bits of the digital input code of the segmented DAC;
• and
• an inter-segment swapping (ISS) circuit, configured to derive a first pre-ISS control code of the higher-significant-bit segment from the first output code, derive a second pre-ISS control code of the lower-significant-bit segment from the second output code, and perform an ISS operation upon the first pre-ISS control code and the second pre-ISS control code to generate a first post-ISS control code of the higher-significant-bit segment and a second post-ISS control code of the lower-significant-bit segment, wherein the first pre-ISS control code comprises first control bits corresponding to the first DAC cells, respectively, the second pre-ISS control code comprises second control bits corresponding to the second DAC cells, respectively, and the ISS operation comprises swapping a first control bit of a first DAC cell included in the higher-significant-bit segment for second control bits of multiple included in the lower-second DAC cells significant-bit segment.