Memories containing an array of read-only memory cells and methods of their fabrication and operation

A method, comprising:

• forming a first conductive region having a first conductivity type in a semiconductor;
• forming a second conductive region having a second conductivity type different than the first conductivity type in the semiconductor overlying the first conductive region;
• forming a plurality of isolation regions in the semiconductor, wherein each isolation region extends from an uppermost surface of the semiconductor to below a bottommost surface of the second conductive region;
• forming a plurality of third conductive regions having the first conductivity type in the semiconductor overlying and in contact with respective portions of the second conductive region between pairs of isolation regions of the plurality of isolation regions;
• forming a dielectric overlying the plurality of third conductive regions and the plurality of isolation regions;
• forming a plurality of conductive contacts extending from an uppermost surface of the dielectric to respective third conductive regions of the plurality of third conductive regions;
• and
• forming a plurality of conductors overlying the dielectric and the plurality of contacts, wherein each conductor of the plurality of conductors is connected to a respective set of contacts of the plurality of contacts.

A method, comprising:

• precharging a plurality of data lines of an array of read-only memory cells to a first voltage level, wherein each data line of the plurality of data lines is connected to an input of a respective latch;
• applying a second voltage level different than the first voltage level to a selected access line of a plurality of access lines of the array of read-only memory cells, wherein each access line of the plurality of access lines is connected to first nodes of a respective plurality of diodes, and wherein the first nodes are selected from a group consisting of cathodes and anodes of its respective plurality of diodes;
• and
• in response to applying the second voltage level to the selected access line, toggling an output of the respective latch of each data line of the plurality of data lines that is connected to a second node of a diode of the respective plurality of diodes for the selected access line.