Multi-die Memory Package with Individually Accessible Command/Address Pins
AssigneeAdvanced Micro Devices, Inc.
InventorAaron John Nygren
Life of this patent
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Abstract
A multi-die memory package with individually accessible command/address (CA) pins is described. In one or more implementations, a memory chip includes a plurality of memory dies arranged in a stacked configuration, a package substrate, and a plurality of command/address pins. Each command/address pin of the plurality of command/address pins is individually accessible via one or more corresponding interconnects to the package substrate or an intermediate component. The intermediate component may be configured to control use of the command/address pins and data pins at the memory chip level.
Claims20
A memory chip, comprising:
- a package substrate;
- and
- a plurality of memory die arranged in a stacked configuration, the plurality of memory die having a plurality of command/address pins, wherein the plurality of command/address pins are individually accessible via interconnects to the package substrate or an intermediate controller.
A method comprising:
- receiving a memory access request for a memory chip comprising a plurality of memory die arranged in a stacked configuration and having a plurality of command/address pins that are individually accessible via interconnects to a package substrate or an intermediate controller of the memory chip;
- and
- controlling, via the interconnects, one or more command/address pins of the plurality of command/address pins to direct one or more data pins of the memory chip to perform a type of memory access at a location of the memory chip to service the memory access request.
A computing system, comprising:
- a processor;
- and
- a memory system communicatively coupled to the processor to service memory access requests of the processor, wherein the memory system includes a memory chip comprising:
- a package substrate;
- and
- a plurality of memory die arranged in a stacked configuration, the plurality of memory die having a plurality of command/address pins, wherein the plurality of command/address pins are individually accessible via interconnects to the package substrate or an intermediate controller of the memory chip.
Dependencies are inferred from the claim text.