Semiconductor package and method of manufacturing the same

A semiconductor package, comprising:

• a base chip including lower connection terminals, upper connection terminals and through-electrodes, the lower connection terminals and the upper connection terminals being opposite to each other, the through-electrodes electrically connecting the lower connection terminals and the upper connection terminals;
• a first semiconductor chip on the base chip, the first semiconductor chip including a first semiconductor substrate, first lower pads, first upper pads, a first passivation layer and first through-vias, the first lower pads in a lower portion of the first semiconductor substrate, the first upper pads in an upper portion of the first semiconductor substrate, the first passivation layer surrounding the first upper pads in the upper portion of the first semiconductor substrate, the first through-vias penetrating through the first semiconductor substrate and electrically connecting the first lower pads and the first upper pads;
• a plurality of second semiconductor chips sequentially stacked on the first semiconductor chip in a first direction, each of the plurality of second semiconductor chips including a second semiconductor substrate, second lower pads, second upper pads, a second passivation layer and second through-vias, the second lower pads in a lower portion of the second semiconductor substrate, the second upper pads in an upper portion of the second semiconductor substrate, the second passivation layer surrounding the second upper pads in the upper portion of the second semiconductor substrate, the second through-vias penetrating through the second semiconductor substrate and electrically connecting the second lower pads and the second upper pads;
• and
• a plurality of connection bumps below the base chip and electrically connected to the lower connection terminals, wherein
• the first lower pads of the first semiconductor chip are in contact with corresponding ones of the upper connection terminals of the base chip, respectively,
• the first upper pads of the first semiconductor chip are in contact with corresponding ones of the second lower pads of a second semiconductor chip that is adjacent to the first semiconductor chip in the first direction, among the plurality of second semiconductor chips, respectively,
• the second upper pads of each of the plurality of second semiconductor chips are in contact with corresponding ones of the second lower pads of an adjacent second semiconductor chip, among the plurality of second semiconductor chips, in the first direction, respectively,
• a width of the first semiconductor substrate of the first semiconductor chip in a horizontal direction is greater than a width of the second semiconductor substrate of the each of the plurality of second semiconductor chips in the horizontal direction, and
• the second semiconductor substrate of the each of the plurality of second semiconductor chips has a width in the horizontal direction that decreases as the second semiconductor substrate being away from the base chip in the first direction.

A semiconductor package, comprising:

• a base chip including lower connection terminals, upper connection terminals and through-electrodes, the lower connection terminals and the upper connection terminals being opposite to each other, the through-electrodes electrically connecting the lower connection terminals and the upper connection terminals;
• and
• a semiconductor chip stack including a plurality of semiconductor chips sequentially stacked on the base chip in a first direction, wherein
• the plurality of semiconductor chips of the semiconductor chip stack comprises
• a first semiconductor chip on the base chip, the first semiconductor chip including first lower pads, first upper pads and first through-vias, the first lower pads and first upper pads being opposite to each other, the first through-vias electrically connecting the first lower pads and the first upper pads, and
• a plurality of second semiconductor chips sequentially stacked on the first semiconductor chip in the first direction, each of the plurality of second semiconductor chips including second lower pads, second upper pads and second through-vias, the second lower pads and second upper pads being opposite to each other, the second through-vias electrically connecting the second lower pads and the second upper pads,
• a plurality of connection bumps below the base chip and electrically connected to the lower connection terminals,
• an encapsulant covering a side surface of the first semiconductor chip and side surfaces of the each of the plurality of second semiconductor chips on the base chip, and
• on at least one side of the semiconductor chip stack, the encapsulant includes a portion in which a width thereof in a horizontal direction increases as the encapsulant being away from the base chip in the first direction.