Semiconductor package

A semiconductor package comprising:

• a first semiconductor chip;
• second semiconductor chips on an upper surface of the first semiconductor chip;
• and
• a molding layer covering at least a portion of the second semiconductor chips on the first semiconductor chip,
• wherein the first semiconductor chip includes:
• a first semiconductor substrate,
• a first upper insulating layer arranged on an upper surface of the first semiconductor substrate,
• a first upper pad arranged within the first upper insulating layer,
• a first lower pad arranged on a lower surface of the first semiconductor substrate, and
• a trench region arranged within the first upper insulating layer;
• wherein each of the second semiconductor chips includes:
• a second semiconductor substrate,
• a second lower pad arranged on a lower surface of the second semiconductor substrate, and
• a second upper pad arranged on an upper portion of the second semiconductor substrate;
• and
• wherein a width in a horizontal direction of each second semiconductor chip is less than a longest width in the horizontal direction of the trench region.

A semiconductor package comprising:

• a first semiconductor chip comprising:
• a first semiconductor substrate,
• a first upper insulating layer including a first insulating layer and a second insulating layer, the first upper insulating layer being disposed on an upper surface of the first semiconductor substrate,
• a first upper pad disposed within the second insulating layer,
• a trench region disposed within the second insulating layer;
• second semiconductor chips on an upper surface of the first semiconductor chip, each of the second semiconductor chips including:
• a second semiconductor substrate,
• a second upper insulating layer disposed on an upper surface of the second semiconductor substrate,
• a second lower insulating layer disposed on a lower surface of the second semiconductor substrate,
• a second upper pad disposed within the second upper insulating layer, and
• a second lower pad disposed within the second lower insulating layer;
• and
• a molding layer covering at least one sidewall of the second semiconductor chips on the first semiconductor chip;
• wherein, in a planar view, the trench region comprises a first region that overlaps the second semiconductor chips and a second region that does not overlap the second semiconductor chips, and
• wherein the trench region has a step-like structure in which vertical levels of the first region and the second region are different from each other.