Semiconductor package

A semiconductor package comprising:

• a substrate including a plurality of insulating layers and a plurality of interconnection layers;
• a semiconductor chip mounted on the substrate;
• and
• a plurality of chip bumps disposed between the substrate and the semiconductor chip,
• wherein:
• the plurality of interconnection layers include an uppermost interconnection layer disposed at an uppermost portion of the substrate and a lowermost interconnection layer disposed in a lowermost portion of the substrate,
• the uppermost interconnection layer includes a first signal pad,
• with respect to a top down view, an area defined by an outermost boundary of the first signal pad is fully included in a first region formed therebelow in the substrate, and
• within the first region in the substrate, no electrically conductive layers are disposed between the first signal pad and the lowermost interconnection layer.

A semiconductor package comprising:

• a substrate including a plurality of insulating layers and a plurality of interconnection layers;
• a semiconductor chip including a plurality of first pads and mounted on the substrate in a first direction;
• a plurality of chip bumps disposed on an upper surface of the substrate;
• and
• a plurality of package bumps disposed on a lower surface of the substrate,
• wherein:
• the plurality of interconnection layers include a plurality of second pads connected to the plurality of first pads and the plurality of chip bumps, and a plurality of third pads connected to the plurality of package bumps, and
• only the plurality of insulating layers are disposed in an overlapping region of the substrate excluding the plurality of third pads, in a region of the substrate overlapping at least one second signal pad in the first direction, among the plurality of second pads.