Semiconductor package

A semiconductor package, comprising:

• a wiring substrate including a plurality of interconnection layers,
• wherein the plurality of interconnection layers comprise:
• a first interconnection layer;
• and
• a second interconnection layer on the first interconnection layer,
• wherein the first interconnection layer comprises first pads, which are spaced apart from each other in a first direction, and first conductive lines, which are disposed between the first pads and are arranged in the first direction,
• wherein the second interconnection layer comprises second pads, which are spaced apart from each other in the first direction, and second conductive lines, which are disposed between the second pads and are arranged in the first direction,
• wherein each of the first and second conductive lines extends lengthwise in a second direction perpendicular to the first direction,
• wherein the first conductive lines comprise first ground lines and first signal lines arranged along a first arrangement pattern,
• wherein the second conductive lines comprise second ground lines and second signal lines arranged along a second arrangement pattern,
• wherein the first arrangement pattern is a pattern in which the first ground line, the first signal line, the first signal line, and the first ground line are repeatedly arranged in the first direction, and
• wherein a number of the second signal lines in the second interconnection layer is different from a number of the first signal lines in the first interconnection layer.

A semiconductor package, comprising:

• a package substrate;
• an interposer on the package substrate;
• and
• a first semiconductor chip and a second semiconductor chip on the interposer,
• wherein the interposer comprises a wiring substrate including a plurality of interconnection layers,
• wherein the plurality of interconnection layers comprise:
• a first interconnection layer;
• and
• a second interconnection layer on the first interconnection layer,
• wherein the first interconnection layer comprises first conductive lines, which include two first ground lines spaced apart from each other in a first direction and two first signal lines interposed therebetween and which extend lengthwise in a second direction perpendicular to the first direction,
• wherein the second interconnection layer comprises second conductive lines including a second signal line, which is adjacent to one of the two first signal lines in a third direction perpendicular to the first and second directions, and a second ground line, which is adjacent to another of the two first signal lines in the third direction,
• wherein the second conductive lines extend lengthwise in the second direction, and
• wherein the first and second semiconductor chips are spaced apart from each other in the second direction.