Semiconductor package with integrated ground lines and signal lines

A semiconductor package comprising:

• a package substrate comprising a first surface and a second surface opposite to each other;
• a first semiconductor chip on the first surface of the package substrate;
• a plurality of memory chips on the first surface of the package substrate;
• a plurality of first signal pads on the first surface of the package substrate and arranged in a first direction, the first direction being a direction parallel to the first surface of the package substrate;
• a plurality of ground pads on the first surface of the package substrate and arranged in the first direction and spaced apart from the plurality of first signal pads in a second direction, respectively, the second direction being a direction parallel to the first surface of the package substrate and intersecting the first direction;
• a plurality of second signal pads on the first surface of the package substrate and arranged in the first direction;
• a plurality of first bonding wires connecting the plurality of first signal pads and the first semiconductor chip, respectively;
• a plurality of second bonding wires connecting the plurality of ground pads and the first semiconductor chip, respectively;
• and
• a plurality of third bonding wires connecting the plurality of second signal pads and the plurality of memory chips, respectively,
• wherein the plurality of first signal pads are disposed between the plurality of ground pads and the plurality of second signal pads, respectively,
• wherein the package substrate comprises:
• a plurality of signal lines connecting the plurality of first signal pads and the plurality of second signal pads, respectively;
• and
• a plurality of ground lines connected to the plurality of ground pads, respectively, and
• wherein at least one of the plurality of ground lines extends between the plurality of ground pads and the plurality of first signal pads in the first direction, respectively.

A semiconductor package comprising:

• a package substrate comprising a first surface and a second surface opposite to each other;
• a first semiconductor chip on the first surface of the package substrate;
• a plurality of memory chips on the first surface of the package substrate and stacked on the first semiconductor chip;
• a plurality of first signal pads arranged in a first direction on the first surface of the package substrate, the first direction being a direction parallel to the first surface of the package substrate;
• a plurality of ground pads arranged in the first direction on the first surface of the package substrate and spaced apart from the plurality of first signal pads, respectively, in a second direction, the second direction being a direction parallel to the first surface of the package substrate and intersecting the first direction;
• a plurality of second signal pads on the first surface of the package substrate and arranged in the first direction;
• a plurality of first bonding wires connecting the plurality of first signal pads and the first semiconductor chip, respectively;
• a plurality of second bonding wires connecting the plurality of ground pads and the first semiconductor chip, respectively;
• and
• a plurality of third bonding wires connecting the plurality of second signal pads and the plurality of memory chips, respectively,
• wherein the plurality of first signal pads are between the plurality of ground pads and the plurality of second signal pads, respectively,
• wherein the package substrate comprises:
• a plurality of signal lines connecting the plurality of first signal pads and the plurality of second signal pads, respectively;
• and
• a plurality of ground lines connected to the plurality of ground pads, and
• wherein at least one of the plurality of ground lines extends between the plurality of ground pads and the plurality of first signal pads in the first direction, respectively.