Semiconductor package

A semiconductor package comprising:

• an interposer;
• a plurality of semiconductor chip stacks arranged on the interposer and each respectively including a plurality of semiconductor chips;
• and
• a bridge chip arranged on the interposer,
• wherein the interposer comprises a second wiring structure, a first wiring structure spaced apart from the second wiring structure in a vertical direction, a first embedded semiconductor chip arranged between the first wiring structure and the second wiring structure, a second embedded semiconductor chip arranged between the first wiring structure and the second wiring structure, the second embedded semiconductor chip spaced apart from the first embedded semiconductor chip in a lateral direction, and a plurality of first conductive posts arranged between the first embedded semiconductor chip and the second embedded semiconductor chip,
• wherein the first embedded semiconductor chip overlaps a first group of semiconductor chips of the plurality of semiconductor chips in the vertical direction, and the second embedded semiconductor chip overlaps a second group of semiconductor chips of the plurality of semiconductor chips in the vertical direction, and
• wherein a first portion of the bridge chip overlaps the first embedded semiconductor chip in the vertical direction, and a second portion of the bridge chip overlaps the second embedded semiconductor chip in the vertical direction.

A semiconductor package comprising:

• an interposer;
• a first semiconductor chip stack arranged on the interposer and including a plurality of first semiconductor chips;
• a second semiconductor chip stack arranged on the interposer and including a plurality of second semiconductor chips, the second semiconductor chip stack spaced apart from the first semiconductor chip stack in a lateral direction;
• a bridge chip arranged on the interposer between the first semiconductor chip stack and the second semiconductor chip stack;
• a first heat dissipation block arranged on the bridge chip between the first semiconductor chip stack and the second semiconductor chip stack;
• and
• a second heat dissipation block on the interposer and configured to extend along an outer edge of the interposer and to extend between the first semiconductor chip stack and the second semiconductor chip stack, and spaced apart from the first heat dissipation block,
• wherein the interposer comprises a second wiring structure, a first wiring structure spaced apart from the second wiring structure in a vertical direction, a first embedded semiconductor chip arranged between the first wiring structure and the second wiring structure, a second embedded semiconductor chip arranged between the first wiring structure and the second wiring structure, the second embedded semiconductor chip apart from the first embedded semiconductor chip in a lateral direction, and a plurality of first conductive posts arranged between the first embedded semiconductor chip and the second embedded semiconductor chip, and a plurality of second conductive posts,
• wherein the plurality of second conductive posts are arranged between the first wiring structure and the second wiring structure, a first group of second conductive posts of the plurality of second conductive posts are arranged between an outer edge of the interposer and the first embedded semiconductor chip, and a second group of second conductive posts of the plurality of second conductive posts are arranged between the outer edge of the interposer and the second embedded semiconductor chip,
• wherein the first wiring structure comprises a first insulating layer and a plurality of first via patterns,
• wherein the first embedded semiconductor chip comprises a plurality of first electrodes extending in a vertical direction inside the first embedded semiconductor chip, and the second embedded semiconductor chip comprises a plurality of second electrodes configured to extend in a vertical direction inside the second embedded semiconductor chip,
• wherein the first wiring structure is in contact with a first surface of the first embedded semiconductor chip and a second surface of the second embedded semiconductor chip, and the second wiring structure is in contact with a third surface of the first embedded semiconductor chip opposite the first surface and a fourth surface of the second embedded semiconductor chip opposite the second surface,
• wherein a first conductive post of the plurality of first conductive posts supplies power to the bridge chip, and a second conductive post of the plurality of second conductive posts supplies power to the first semiconductor chip stack, and
• wherein each of a first active surface of the first embedded semiconductor chip and a second active surface of the second embedded semiconductor chip is arranged closer to the first wiring structure than to the second wiring structure.