Semiconductor package with alignment mark and method of fabricating the same

A semiconductor package, comprising:

• a first semiconductor chip;
• and
• a second semiconductor chip on the first semiconductor chip,
• wherein the first semiconductor chip comprises:
• a substrate,
• a semiconductor device provided on a first surface of the substrate,
• an interconnection layer on the first surface of the substrate,
• an insulating layer covering a second surface of the substrate that is opposite to the first surface of the substrate;
• a first via penetrating the substrate and the insulating layer in a first direction that is perpendicular to the first surface of the substrate,
• a connection pattern on a surface of the insulating layer and connected to the first via, and
• a passivation layer on the surface of the insulating layer to such that the passivation layer covers at least a portion of the connection pattern,
• wherein a surface of the first via is placed at a level lower than the surface of the insulating layer,
• wherein the first semiconductor chip further comprises a signal region and a dummy region enclosing the signal region, and
• wherein the connection pattern comprises:
• a first pattern connected to the first via, and
• an alignment pattern on the dummy region,
• the alignment pattern is disconnected from the semiconductor device, and
• the alignment pattern is placed at a same level as the first pattern.

A semiconductor package, comprising:

• a first semiconductor chip;
• and
• a second semiconductor chip on the first semiconductor chip,
• wherein the first semiconductor chip comprises:
• a substrate,
• a semiconductor device on a first surface of the substrate,
• an interconnection layer on the first surface of the substrate,
• an insulating layer covering at least a portion of a second surface of the substrate that is opposite to the first surface of the substrate,
• a first via and a second via penetrating the substrate and the insulating layer in a first direction that is perpendicular to the first surface of the substrate,
• a connection pattern on a surface of the insulating layer, the connection pattern comprising a first pattern connected to the first via and a second pattern connected to the second via, and
• a passivation layer on the surface of the insulating layer to cover the second pattern and to expose the first pattern,
• wherein the first via is connected to the semiconductor device,
• wherein the second via is disconnected from the semiconductor device, and
• wherein a surface of the second via is located at a level lower than a surface of the insulating layer.