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US 2026/0107764 A1Published application
Capacitors with electrically inactive metal layers
AssigneeGlobalfoundries Singapore Pte. Ltd.
InventorsWANBING YI, EE JAN KHOR
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Abstract
The disclosed subject matter relates generally to structures in semiconductor devices and integrated circuit (IC) chips. More particularly, the present disclosure relates to a metal-dielectric-metal capacitor having electrically inactive metal layers arranged in an interconnect level that is below another interconnect level containing two sets of metal lines interdigitated with each other.
Claims20
A structure in a semiconductor device comprising:
- a first interconnect level above a substrate;
- a first plurality of metal layers in the first interconnect level, wherein the metal layers in the first plurality of metal layers are electrically inactive;
- a second interconnect level above the first interconnect level;
- and
- a second plurality of metal layers in the second interconnect level, the second plurality of metal layers comprises a first set of metal lines interdigitated with a second set of metal lines, and
- wherein each metal layer in the first plurality of metal layers is only aligned vertically below each metal line in the first set of metal lines of the second plurality of metal layers.
3 more elements
A structure in a semiconductor device comprising:
- a first interconnect level above a substrate;
- a first plurality of metal layers in the first interconnect level, wherein the metal layers in the first plurality of metal layers are electrically inactive;
- a second interconnect level above the first interconnect level;
- and
- a second plurality of metal layers in the second interconnect level,
- wherein each metal layer in the first plurality of metal layers is positioned equidistant to two immediately adjacent metal layers in the second plurality of metal layers.
3 more elements
Dependencies are inferred from the claim text.