Semiconductor package and method of manufacturing the semiconductor package

A semiconductor package, comprising:

• an interposer;
• a semiconductor chip on the interposer, the semiconductor chip including a substrate having a first surface facing the interposer and a second surface opposing the first surface, a front insulating layer on the first surface of the substrate, and a measurement via pattern portion in a peripheral region of the substrate;
• and
• a sealing member covering the semiconductor chip, wherein
• the sealing member is on the interposer and exposes the second surface of the substrate,
• wherein the measurement via pattern portion includes corner measurement pattern portions respectively provided at four corner portions of the substrate,
• wherein each of the corner measurement pattern portions includes first dummy via structures and a second dummy via structures,
• wherein the first dummy via structures extend in a thickness direction from the first surface of the substrate to the second surface such that end portions of the first dummy via structures are exposed from the second surface of the substrate, and
• wherein the second dummy via structures extend in the thickness direction from the first surface of the substrate to a depth in the substrate such that end portions of the second dummy via structures are not exposed from the second surface of the substrate.

A semiconductor package, comprising:

• a first semiconductor chip;
• a second semiconductor chip on the first semiconductor chip, the second semiconductor chip having a central region and a peripheral region surrounding the central region, the second semiconductor chip including a measurement via pattern portion in the peripheral region;
• and
• a sealing member covering the second semiconductor chip, the sealing member being on the first semiconductor chip and exposing an upper surface of the second semiconductor chip,
• wherein the measurement via pattern portion includes corner measurement pattern portions respectively provided at four corner portions of the second semiconductor chip and side measurement pattern portions respectively provided at four side portions of the second semiconductor chip, and
• wherein each of the corner measurement pattern portions and the side measurement pattern portions includes first dummy via structures and second dummy via structures,
• wherein the first dummy via structures extend into at least a portion of the second semiconductor chip in a thickness direction such that end portions of the first dummy via structures are exposed from the upper surface of the second semiconductor chip, and
• wherein the second dummy via structures extend partially through the second semiconductor chip in the thickness direction such that end portions of the second dummy via structures are not exposed from the upper surface of the second semiconductor chip.