Semiconductor device and method of manufacturing semiconductor device

A semiconductor device comprising:

• a first conductive line extending in a first direction;
• a second conductive line positioned on the first conductive line and extending in a second direction that intersects the first direction;
• and
• a memory cell positioned between the first conductive line and the second conductive line, and including a lower electrode pattern, an upper electrode pattern positioned on the lower electrode pattern, and a variable resistance pattern positioned between the lower electrode pattern and the upper electrode pattern,
• wherein the upper electrode pattern comprises:
• a first portion positioned between the variable resistance pattern and the second conductive line;
• a pair of second portions extending on first sidewalls of the variable resistance pattern that face each other and are arranged in the second direction;
• and
• a pair of third portions extending on second sidewalls of the variable resistance pattern that face each other and are arranged in the first direction, and on sidewalls of the second conductive line that face each other and are arranged in the first direction, and
• wherein the second portions and the third portions of the upper electrode pattern surround an interface between the first portion and the variable resistance pattern.

A method of manufacturing a semiconductor device, the method comprising:

• sequentially forming a lower electrode layer, a variable resistance layer, and an upper electrode layer on a first conductive layer;
• forming upper electrode lines each extending in a first direction by etching the upper electrode layer;
• partially etching the variable resistance layer;
• forming a first additional electrode layer along a profile of the upper electrode lines and the variable resistance layer;
• and
• forming variable resistance lines by further etching the variable resistance layer.