Three-dimensional system-on-chip device

A three-dimensional (3D) system-on-chip (SOC) device comprising:

• an intermediate redistribution layer having a top surface and a bottom surface;
• a lower semiconductor module located on said bottom surface of said intermediate redistribution layer;
• and
• an upper semiconductor module located on said top surface of said intermediate redistribution layer;
• wherein said intermediate redistribution layer electrically connects said lower semiconductor module to said upper semiconductor module and further connects to an external power source;
• wherein said lower semiconductor module includes:
• a lower dielectric layer that is located on said bottom surface of said intermediate redistribution layer;
• a lower insulating layer that is located on a surface of said dielectric layer oppositely from said intermediate redistribution layer, and that includes a plurality of openings spaced apart from each other;
• a plurality of lower conductive posts that pass through said lower dielectric layer, and that respectively correspond in position to some of said openings, each of said lower conductive posts having an end that is exposed from the corresponding one of said openings, and another end that is electrically connected with said intermediate redistribution layer;
• and
• a lower chip unit composed of a plurality of SoC processing chips, and located in said lower dielectric layer, each of said SoC processing chips being located between adjacent ones of said lower conductive posts;
• wherein each of said SoC processing chips includes:
• a first processor redistribution layer which has a plurality of electrode pads exposed from said openings;
• a first processor substrate which is disposed on said first processor redistribution layer and which has a plurality of first vias formed through said first processor substrate;
• a processor active layer formed on said first processor substrate and connected to said first processor redistribution layer through said first vias,
• a second processor redistribution layer disposed on and electrically connected to said processor active layer;
• a processor dielectric layer disposed on and connected to said second processor redistribution layer;
• a second processor substrate disposed on and connected to said processor dielectric layer;
• and
• a plurality of second vias which pass through said processor dielectric layer and said second processor substrate and each of which electrically connects with said second processor redistribution layer and said intermediate redistribution layer;
• wherein said lower semiconductor module further includes a plurality of solder balls which are respectively disposed in said opening and which respectively electrically connect said electrode pads of said processor chip and said lower conductive posts;
• and
• wherein said upper semiconductor module includes:
• an upper encapsulating layer formed on said upper surface of said intermediate redistribution layer, and
• a plurality of stacked memory units that are embedded in said upper encapsulating layer in a spaced apart manner, and that are arranged in an array, each of said stacked memory units having an upper redistribution layer electrically connected to said intermediate redistribution layer, and a memory chip stack electrically connected to said upper redistribution layer.