Semiconductor package

A semiconductor package comprising:

• a package substrate;
• a first semiconductor chip on the package substrate;
• a conductive connector between the package substrate and the first semiconductor chip, the conductive connector electrically connecting the package substrate to the first semiconductor chip;
• a second semiconductor chip over the first semiconductor chip, the second semiconductor chip being spaced apart from the first semiconductor chip in a vertical direction perpendicular to an upper surface of the substrate;
• a vertical bonding wire extending in the vertical direction between the package substrate and the second semiconductor chip;
• a bonding layer contacting an upper surface of the second semiconductor chip;
• and
• a third semiconductor chip contacting an upper surface of the bonding layer,
• wherein a distance between the first semiconductor chip and the second semiconductor chip in the vertical direction is less than a thickness of the bonding layer in the vertical direction.

A semiconductor package comprising:

• a package substrate;
• a first semiconductor chip on the package substrate;
• a conductive connector between the package substrate and the first semiconductor chip, the conductive connector electrically connecting the package substrate to the first semiconductor chip;
• a second semiconductor chip contacting an upper surface of the first semiconductor chip;
• a vertical bonding wire between the package substrate and the second semiconductor chip, the vertical bonding wire extending in a vertical direction perpendicular to an upper surface of the package substrate, having an upper surface coplanar with the upper surface of the first semiconductor chip, and electrically connecting the package substrate to the second semiconductor chip;
• a first bonding layer contacting an upper surface of the second semiconductor chip;
• a third semiconductor chip contacting an upper surface of the first bonding layer;
• a first bonding wire electrically connecting the third semiconductor chip to the package substrate;
• a second bonding layer contacting an upper surface of the third semiconductor chip;
• a fourth semiconductor chip contacting an upper surface of the second bonding layer;
• and
• a second bonding wire electrically connecting the fourth semiconductor chip to the package substrate.