Semiconductor package

A semiconductor package comprising:

• a semiconductor chip comprising:
• a substrate comprising a front surface and a back surface opposite to the front surface;
• front pads on the front surface;
• through-electrodes electrically connected to the front pads and penetrating through the substrate and protruding to the back surface;
• and
• back pads on the through-electrodes;
• a side passivation layer surrounding the semiconductor chip;
• a dielectric layer covering at least a portion of each of the semiconductor chip and the side passivation layer, and surrounding the through-electrodes and the back pads on the back surface of the substrate;
• a top semiconductor chip on the dielectric layer, the top semiconductor chip comprising connection pads electrically connected to the back pads;
• and
• bump structures below the semiconductor chip and connected to the front pads,
• wherein the side passivation layer comprises an upper surface and a lower surface opposite to the upper surface,
• wherein the upper surface of the side passivation layer and the back surface of the substrate extend in a same direction, and
• wherein a first distance between the back surface of the substrate and a top surface of the dielectric layer is greater than a second distance between the upper surface of the side passivation layer and the top surface of the dielectric layer.

A semiconductor package comprising:

• a semiconductor chip comprising:
• a substrate comprising a front surface and a back surface opposite to the front surface;
• front pads on the front surface;
• through-electrodes electrically connected to the front pads and penetrating through the substrate and protruding to the back surface;
• and
• back pads disposed on the through-electrodes;
• a side passivation layer surrounding the semiconductor chip and spaced from the through-electrodes in a horizontal direction;
• a dielectric layer covering at least a portion of each of the semiconductor chip and the side passivation layer, and surrounding the through-electrodes and the back pads on the back surface of the substrate;
• and
• a top semiconductor chip on the semiconductor chip and the dielectric layer, the top semiconductor chip comprising connection pads contacting the back pads.