Low cost wafer level packages and silicon

A wafer-level package, comprising:

• a first integrated circuit die including a front side with a plurality of pads;
• a second integrated circuit die including a front side with a plurality of pads, wherein an adhesive layer affixes a back side of the second integrated circuit die to the front side of the first integrated circuit die;
• a resin layer surrounding edge sides of the second integrated circuit die and the front side of the second integrated circuit die, and surrounding the front side of the first integrated circuit die, wherein the resin layer includes an activatable catalyst material;
• a solder resist layer having a back surface in contact with a front surface of the resin layer;
• and
• a redistribution layer comprising:
• first activated and metallized portions of the resin layer adjacent the plurality of pads on the front side of the second integrated circuit die;
• second activated and metallized portions of the resin layer adjacent the plurality of pads on the front side of the first integrated circuit die;
• and
• third activated and metallized portions of the resin layer extending from given ones of the first activated and metallized portions of the resin layer, down the edge sides of the second integrated circuit die, and across portions of the resin layer on the front side of the first integrated circuit die, to thereby electrically connection given ones of the plurality of pads on the front side of the second integrated circuit die to locations on the resin layer on the front side of the first integrated circuit die.