Semiconductor package

A semiconductor package comprising:

• a first semiconductor chip;
• a molding layer surrounding the first semiconductor chip;
• a first conductive post extending through the molding layer on one side of the first semiconductor chip;
• and
• a substrate on the molding layer and the first semiconductor chip,
• wherein the first conductive post comprises:
• a first post;
• a second post on the first post and in contact with a first upper surface of the first post;
• and
• a first seed layer on a first lower surface of the first post, and
• wherein the second post has a tapered shape in which a width thereof decreases toward the first post.

A semiconductor package comprising:

• a semiconductor chip;
• a molding layer surrounding the semiconductor chip;
• a conductive post extending through the molding layer on one side of the semiconductor chip;
• and
• a substrate on the molding layer and the semiconductor chip and having a substrate wiring pattern connected to the conductive post and the semiconductor chip,
• wherein the conductive post comprises:
• a first post;
• a seed layer on a lower surface and an outer circumferential surface of the first post;
• and
• a second post on the first post and in contact with a first upper surface of the first post,
• wherein a width of the first post is greater than a width of the second post on a contact surface of the first post and the second post,
• wherein a width of a lower surface of the second post is smaller than a width of an upper surface of the second post, and
• wherein an outer circumferential surface of the second post is in contact with the molding layer.