Semiconductor package including a dam structure

A semiconductor package, comprising:

• a package substrate;
• a first semiconductor chip disposed on an upper surface of the package substrate such that a first surface on which first chip pads are formed faces upward;
• a dam structure disposed within a pad free region on the first surface of the first semiconductor chip, wherein the pad free region does not include first chip pads therein;
• a first spacer chip attached to the upper surface of the package substrate, wherein the first spacer chip is spaced apart from the first semiconductor chip along a first direction;
• a plurality of second semiconductor chips sequentially stacked on the first spacer chip using adhesive films;
• first bonding wires electrically connecting each of the first chip pads of the first semiconductor chip to each of first substrate pads of the package substrate, respectively;
• second bonding wires electrically connecting each of second chip pads of the plurality of second semiconductor chips to each of second substrate pads of the package substrate, respectively;
• and
• a molding disposed on the package substrate, the first semiconductor chip and the plurality of second semiconductor chips,
• wherein a lowermost second semiconductor chip among the plurality of second semiconductor chips is attached to the first semiconductor chip by a first adhesive film among the adhesive films, and
• wherein the dam structure is embedded in the first adhesive film.

A semiconductor package, comprising:

• a package substrate extending in a first direction, and including a plurality of substrate pads disposed on an upper surface thereof;
• a first semiconductor chip disposed on the upper surface of the package substrate such that a first surface where first chip pads are formed faces upward, wherein the first semiconductor chip includes a pad region on which the first chip pads are disposed and a pad free region on which the first chip pads are not disposed;
• a dam structure disposed within the pad free region on the first surface of the first semiconductor chip;
• first and second spacer chips attached to the upper surface of the package substrate, wherein the first and second spacer chips are spaced apart from each other along the first direction with the first semiconductor chip interposed between the first and second spacer chips;
• third and fourth spacer chips attached to the upper surface of the package substrate, wherein the third and fourth spacer chips are spaced apart from each other along a second direction perpendicular to the first direction with the first semiconductor chip interposed between the third and fourth spacer chips;
• a plurality of second semiconductor chips sequentially stacked on the first, second, third and fourth spacer chips by adhesive films;
• first bonding wires electrically connecting each of the first chip pads of the first semiconductor chip to each of the plurality of substrate pads, respectively;
• second bonding wires electrically connecting each of second chip pads of the plurality of second semiconductor chips to each of the plurality of substrate pads, respectively;
• and
• a molding disposed on the package substrate covering the first, second, third and fourth spacer chips, the first semiconductor chip, and the plurality of second semiconductor chips,
• wherein a lowermost second semiconductor chip among the plurality of second semiconductor chips is attached to the first semiconductor chip by a first adhesive film among the adhesive films, and
• wherein the dam structure is embedded in the first adhesive film.