Semiconductor package including conductive post

A semiconductor package comprising:

• a lower redistribution structure including a lower redistribution layer;
• a lower chip structure disposed on the lower redistribution structure, the lower chip structure electrically connected to the lower redistribution layer;
• conductive posts arranged on the lower redistribution structure in a first horizontal direction, the conductive posts spaced apart from the lower chip structure in a second horizontal direction, intersecting the first horizontal direction;
• and
• an encapsulant covering the lower chip structure and the conductive posts,
• wherein in a plan view, a pattern density of the conductive posts decreases as a distance from a center of the lower chip structure increases,
• the conductive posts include a first conductive post and a second conductive post farther from the center of the lower chip structure than the first conductive post, and
• a cross-sectional area of the first conductive post is greater than a cross-sectional area of the second conductive post, and the first conductive post has a shape, different from that of the second conductive post.

A semiconductor package comprising:

• a lower redistribution structure including a lower redistribution layer;
• a bump structure disposed below the lower redistribution structure, the bump structure electrically connected to the lower redistribution layer;
• and
• a connection structure disposed on the lower redistribution structure,
• wherein the connection structure includes a lower chip structure electrically connected to the lower redistribution layer, conductive posts disposed around the lower chip structure, and an encapsulant covering the lower chip structure and the conductive posts,
• upper surfaces of the conductive posts are coplanar with the encapsulant, and
• in a plan view, the connection structure includes a plurality of regions arranged in a first horizontal direction,
• the plurality of regions are spaced apart from the lower chip structure in a second horizontal direction, intersecting the first horizontal direction,
• the plurality of regions include a first region and a second region, farther from a center of the lower chip structure than the first region,
• a pattern density of the conductive posts in the second region is lower than a pattern density of the conductive posts in the first region, and
• the conductive posts in the second region have a circular shape, and the conductive posts in the first region have a rectangular shape.