Semiconductor package

A semiconductor package comprising:

• a bridge die;
• a lower insulating layer below the bridge die;
• lower redistribution layers including external redistribution layers, internal redistribution layers, and connection redistribution layers, the external redistribution layers on the lower insulating layer, the internal redistribution layers in the lower insulating layer, and the connection redistribution layers connected to the bridge die;
• and
• an under bump metallization (UBM) structure spaced apart from the bridge die in a horizontal direction, at least portion of the UBM structure passing through the lower insulating layer,
• wherein each of the external redistribution layers has a lower surface in contact with an upper surface of the lower insulating layer, and has an increasing width with distance approaching the upper surface of the lower insulating layer, and
• each of the internal redistribution layers has an upper surface at a same or lower level as the upper surface of the lower insulating layer, and each of the internal redistribution layers has a decreasing width with distance from the upper surface of the lower insulating layer.

A semiconductor package comprising:

• a package substrate;
• semiconductor chips;
• and
• an interposer substrate between the package substrate and the semiconductor chips, the interposer substrate electrically connecting the semiconductor chips to the package substrate and including
• a lower redistribution structure including a lower insulating layer and an under bump metallization (UBM) structure passing through the lower insulating layer,
• a bridge die on the lower redistribution structure, the bridge die spaced apart from the UBM structure and electrically connected to the semiconductor chips,
• an encapsulant on the lower redistribution structure and covering at least a portion of the bridge die and at least a portion of the UBM structure,
• an upper redistribution structure on the encapsulant, the upper redistribution structure including upper redistribution layers electrically connected to the semiconductor chips, and
• a conductive post passing through the encapsulant, the conductive post electrically connecting the upper redistribution layers and the UBM structure,
• wherein the UBM structure includes
• a first portion at a level closer to an upper surface of the lower insulating layer than to an upper surface of the UBM structure, the first portion having a maximum width in a horizontal direction,
• a second portion above the first portion and having a width decreasing with distance from the first portion, and
• a third portion below the first portion and having a width decreasing with distance from the first portion.