Semiconductor package and manufacturing method thereof

A semiconductor package comprising:

• a first semiconductor chip having a first upper surface which is an active surface and a first lower surface opposite to the first upper surface and having a through-electrode arranged in the first semiconductor chip;
• a second semiconductor chip stacked on the first semiconductor chip, the second semiconductor chip having a second lower surface which is an active surface and a second upper surface opposite to the second lower surface and having a larger size than the first semiconductor chip in a horizontal direction;
• a sealant sealing the first semiconductor chip on a lower surface of the second semiconductor chip;
• an external through-electrode placed below the second semiconductor chip and adjacent to the first semiconductor chip, the external through-electrode penetrating the sealant;
• and
• external connection terminals respectively arranged on a lower surface of the external through-electrode and a lower surface of a first lower pad disposed on the first lower surface of the first semiconductor chip,
• wherein the second semiconductor chip is stacked on the first semiconductor chip through hybrid copper bonding (HCB), and
• the lower surface of the external through-electrode is substantially coplanar with the lower surface of the first lower pad.

A semiconductor package comprising:

• a package substrate;
• a first semiconductor device on the package substrate;
• and
• at least one second semiconductor device placed on the package substrate and adjacent to the first semiconductor device,
• wherein the first semiconductor device has a package structure including a first semiconductor chip having a first upper surface as an active surface and a first lower surface opposite to the first upper surface and having a through-electrode arranged in the first semiconductor chip, a second semiconductor chip stacked on the first semiconductor chip, having a second lower surface as an active surface and a second upper surface opposite to the second lower surface, and having a larger size than the first semiconductor chip in a horizontal direction, and an external through-electrode placed below the second semiconductor chip and adjacent to the first semiconductor chip, and
• the second semiconductor chip is stacked on the first semiconductor chip through hybrid copper bonding (HCB).