Semiconductor package with stacked semiconductor chip structure

A semiconductor package comprising:

• a package substrate;
• a first semiconductor chip structure comprising a first semiconductor chip mounted on the package substrate;
• a second semiconductor chip structure comprising a second semiconductor chip stacked on the first semiconductor chip structure to form a stepped shape in a first direction;
• and
• a substrate alignment key on a surface of the package substrate, the substrate alignment key having a first alignment surface parallel to the first direction and a second alignment surface parallel to a second direction perpendicular to the first direction,
• wherein the first semiconductor chip structure comprises a first alignment key on an active surface of the first semiconductor chip, the first alignment key having a first surface parallel to the first direction and a second surface parallel to the second direction,
• wherein the second semiconductor chip structure comprises a second alignment key on an active surface of the second semiconductor chip, the second alignment key having a third surface parallel to the first direction and a fourth surface parallel to the second direction,
• wherein a surface of the first semiconductor chip, which is parallel to the second direction, is aligned with the second alignment surface of the substrate alignment key, and
• wherein a surface of the first semiconductor chip, which is parallel to the first direction, is aligned with the first alignment surface of the substrate alignment key.

A semiconductor package comprising:

• a package substrate;
• a plurality of semiconductor chip structures comprising semiconductor chips stacked on the package substrate and offset from each other in an first direction to form a stepped shape;
• and
• a substrate alignment key on an active surface of the package substrate, the substrate alignment key having a first alignment surface parallel to the first direction and a second alignment surface parallel to a second direction perpendicular to the first direction,
• wherein each of the plurality of semiconductor chip structures comprises:
• an alignment key, and
• a passivation layer extending along a surface of a respective semiconductor chip, the alignment key being buried in the passivation layer,
• wherein a surface, parallel to the second direction, of a semiconductor chip of a semiconductor chip structure of the plurality of semiconductor chip structures closest to the package substrate is aligned with the second alignment surface of the substrate alignment key, and
• a surface, parallel to the first direction, of the semiconductor chip structure of the plurality of semiconductor chip structures closest to the package substrate is aligned with the first alignment surface of the substrate alignment key.