Semiconductor package

A semiconductor package comprising:

• a first semiconductor chip including a first substrate including a bonding region and an align key region;
• a first bonding layer including a first inner bonding layer and a first outer bonding layer sequentially stacked on the first semiconductor chip along a vertical direction with respect to an upper surface of the first substrate;
• a second bonding layer disposed on the first bonding layer;
• and
• a second semiconductor chip disposed on the second bonding layer and including a second substrate,
• wherein a first thickness in the vertical direction of the first inner bonding layer on the bonding region of the first substrate is greater than a second thickness in the vertical direction of the first inner bonding layer on the align key region of the first substrate, and
• wherein a third thickness in the vertical direction of the first outer bonding layer on the bonding region of the first substrate is smaller than a fourth thickness in the vertical direction of the first outer bonding layer on the align key region of the first substrate.

A semiconductor package comprising

• a buffer die including a substrate having a bonding region and an align key region;
• memory dies sequentially stacked on the buffer die;
• a first bonding layer structure interposed between the buffer die and a lowermost one of the memory dies;
• and
• a second bonding layer structure interposed between the memory dies,
• wherein the first bonding layer structure includes:
• a first bonding layer including a first inner bonding layer and a first outer bonding layer sequentially stacked on an upper surface of the substrate;
• first inner bonding pads accommodated in the first inner bonding layer on the bonding region of the substrate;
• first inner align key patterns accommodated in the first inner bonding layer on the align key region of the substrate;
• first outer bonding pads accommodated in the first outer bonding layer on the bonding region of the substrate and respectively in contact with the first inner bonding pads;
• and
• first outer align key patterns accommodated in the first outer bonding layer on the align key region of the substrate, and
• wherein a first pattern density, which is a ratio of a total planar area of the first inner bonding pads to a planar area of the portion of the first inner bonding layer that is on the bonding region of the substrate, is less than a second pattern density, which is a ratio of a total planar area of the first inner align key patterns to a planar area of a portion of the first inner bonding layer that is on the align key region of the substrate, and
• wherein a third pattern density, which is a ratio of a total planar area of the first outer bonding pads to a planar area of the portion of the first outer bonding layer that is on the bonding region of the substrate, is greater than a fourth pattern density, which is a ratio of a total planar area of the first outer align key patterns to a planar area of the portion of the first outer bonding layer that is on the align key region of the substrate.