Back-to-back stacked silicon-based capacitors in a package substrate for a system-on-chip

A system comprising:

• a package substrate comprising a core layer including plated-through holes;
• at least one die mounted on top of the package substrate, wherein the at least one die includes a first voltage domain and a second voltage domain, wherein during operation of the system the first voltage domain requires faster changes in power than the second voltage domain;
• and
• a set of back-to-back stacked silicon-based capacitors formed within the core layer of the package substrate, wherein the set of back-to-back stacked silicon-based capacitors are formed in slots within the core layer in regions excluding the plated-through holes, wherein the set of back-to-back stacked silicon-based capacitors comprises a first set of silicon-based capacitors stacked on a respective second set of silicon-based capacitors, and wherein the first set of the silicon-based capacitors are coupled to components within the first voltage domain, and wherein the second set of the silicon-based capacitors are coupled to components within the second voltage domain.

A method comprising:

• providing a package substrate comprising a core layer including plated-through holes;
• mounting at least one die on top of the package substrate, wherein the at least one die includes at least one voltage domain;
• and
• providing a set of back-to-back stacked silicon-based capacitors formed within the core layer of the package substrate, wherein the set of back-to-back stacked silicon-based capacitors are formed in slots within the core layer in regions excluding the plated-through holes, and wherein a subset of the set of back-to-back stacked silicon-based capacitors are coupled to components within the at least one voltage domain to manage an impedance associated with the at least one voltage domain.