Semiconductor package

A semiconductor package comprising:

• a redistribution substrate comprising a redistribution layer;
• a first semiconductor chip on the redistribution substrate;
• a first molding film surrounding the first semiconductor chip on the redistribution substrate;
• a second semiconductor chip above the first semiconductor chip;
• a passivation film extending along a side surface of the second semiconductor chip and an upper surface of the second semiconductor chip above the first molding film;
• a shielding wall structure penetrating the first molding film and surrounding a side surface of the first semiconductor chip, the shielding wall structure being connected to the redistribution layer;
• a shielding film structure extending along the passivation film above the side surface of the second semiconductor chip and the upper surface of the second semiconductor chip, the shielding film structure being connected to the shielding wall structure;
• and
• a second molding film covering the shielding film structure above the first molding film.

A semiconductor package comprising:

• a redistribution substrate;
• a first semiconductor chip on the redistribution substrate;
• a shielding wall structure on the redistribution substrate and surrounding a side surface of the first semiconductor chip;
• a second semiconductor chip above the first semiconductor chip;
• a wiring post between the first semiconductor chip and the shielding wall structure and electrically connecting the redistribution substrate and the second semiconductor chip;
• a passivation film extending along a side surface of the second semiconductor chip and an upper surface of the second semiconductor chip;
• a shielding film structure extending along the passivation film and connected to the shielding wall structure;
• a first chip penetration via penetrating at least a portion of the first semiconductor chip and connected to the second semiconductor chip;
• a first chip bonding pad between the first semiconductor chip and the second semiconductor chip and connected to the first chip penetration via;
• and
• a second chip bonding pad between the first semiconductor chip and the second semiconductor chip and adjacent to a lower portion of the second semiconductor chip, the second chip bonding pad contacting the first chip bonding pad.