Semiconductor devices and data storage systems including the same

A semiconductor device, comprising:

• a conductive layer;
• a stack structure on the conductive layer, wherein the stack structure includes a first region, a second region, and a third region that is between the first region and the second region in a first direction that is parallel with an upper surface of the conductive layer, wherein the stack structure includes memory gate electrodes and upper gate electrodes that are stacked and spaced apart from each other in a second direction that is perpendicular to the upper surface of the conductive layer, and wherein ones of the upper gate electrodes extend to different lengths in the first direction in the third region and the ones of the upper gate electrodes include pad regions, respectively;
• an insulating layer on the stack structure;
• isolation regions that extend into the upper gate electrodes in the first direction in the first region and the third region;
• a channel structure that extends into the stack structure in the second direction in the first region;
• first contact structures that extend into the insulating layer in the second direction, wherein the first contact structures are electrically connected to the pad regions of the ones of the upper gate electrodes, respectively, in the third region;
• second contact structures that extend into the upper gate electrodes, the insulating layer, and at least one of the memory gate electrodes, wherein the second contact structures are electrically connected to the memory gate electrodes, respectively, in the second region, and wherein respective upper surfaces of the second contact structures are coplanar with respective upper surfaces of the first contact structures;
• first studs on the first contact structures;
• and
• second studs on the second contact structures,
• wherein respective upper surfaces of the first studs are coplanar with respective upper surfaces of the second studs, and
• wherein respective lower surfaces of the first studs are coplanar with respective lower surfaces of the second studs.

A data storage system, comprising:

• a semiconductor storage device that includes a first semiconductor structure that includes circuit devices, a second semiconductor structure on the first semiconductor structure, and an input/output pad that is electrically connected to the circuit devices;
• and
• a controller that is electrically connected to the semiconductor storage device through the input/output pad, wherein the controller is configured to control the semiconductor storage device,
• wherein the second semiconductor structure comprises:
• a conductive layer;
• a stack structure on the conductive layer, wherein the stack structure includes a first region, a second region, and a third region that is between the first region and the second region in a first direction that is parallel with an upper surface of the conductive layer, wherein the stack structure includes lower gate electrodes, memory gate electrodes, and upper gate electrodes that are stacked and spaced apart from each other in a second direction that is perpendicular to the upper surface of the conductive layer, and wherein ones of the upper gate electrodes extend to different lengths from one another in the first direction in the third region and include pad regions;
• an insulating layer on the stack structure;
• a channel structure that extends into the stack structure in the second direction in the first region;
• first contact plugs that extend into the insulating layer in the second direction, wherein the first contact plugs are electrically connected to the pad regions of the upper gate electrodes, respectively, in the third region;
• second contact plugs that extend into at least one among the upper gate electrodes, the memory gate electrodes, and the lower gate electrodes and the insulating layer in the second direction, wherein ones of the second contact plugs extend to different lengths from one another in the second direction and are electrically connected to the lower gate electrodes and/or the memory gate electrodes, respectively, in the second region;
• a side-surface insulating structure that extends around a side surface of each of the second contact plugs in the second region;
• and
• an upper side-surface insulating layer that extends around a side surface of each of the first contact plugs in the third region.