Back-side power rail device and method of making same

A semiconductor device structure, comprising:

• a device layer disposed over a front-side of a substrate;
• a first interconnect structure disposed over the device layer, the first interconnect structure including a first conductive feature;
• a first dielectric layer disposed over the first interconnect structure;
• a compressive material layer disposed over the first dielectric layer;
• a bonding layer disposed over the first dielectric layer and the compressive material layer;
• a carrier substrate bonded with the bonding layer;
• one or more back-side vias coupled with the device layer opposite the first interconnect structure;
• a second interconnect structure disposed over the device layer and the one or more back-side vias;
• and
• one or more second conductive features disposed over the second interconnect structure.

A method of forming a back-side power rail device, comprising:

• forming a device layer over a front-side of a substrate;
• forming a first interconnect structure over the device layer, the first interconnect structure including a first conductive feature;
• forming a first dielectric layer over the first interconnect structure;
• forming a compressive material layer over the first dielectric layer,
• wherein the compressive material layer is aligned with the first conductive feature in a direction extending between the front-side and back-side of the substrate, and
• wherein a border of the compressive material layer extends outside a border of the first conductive feature to compensate for shrinkage of the compressive material layer;
• forming a bonding layer over the first dielectric layer and the compressive material layer;
• bonding a carrier substrate with the bonding layer;
• removing, from a back-side of the substrate, at least a portion of the substrate to expose the device layer;
• forming one or more back-side vias coupled with the device layer opposite the first interconnect structure;
• and
• forming a second interconnect structure over the device layer and the one or more back-side vias to be coupled with a back-side power rail.