Semiconductor package

A semiconductor package comprising:

• a first semiconductor chip including:
• a first semiconductor substrate having a first active surface and a first inactive surface opposite to the first active surface,
• a plurality of first through-electrodes passing through the first semiconductor substrate,
• a plurality of package connection pads connected to the plurality of first through-electrodes on the first active surface of the first semiconductor substrate,
• a first front insulation layer surrounding the plurality of package connection pads on the first active surface of the first semiconductor substrate, and
• a first backside insulation layer covering the first inactive surface of the first semiconductor substrate;
• a plurality of second semiconductor chips, each second semiconductor chip of the plurality of second semiconductor chips including:
• a second semiconductor substrate having a second active surface and a second inactive surface opposite to the second active surface,
• a plurality of second through-electrodes passing through the second semiconductor substrate,
• a second front insulation layer on the second active surface of the second semiconductor substrate, and
• a second backside insulation layer covering the second inactive surface of the second semiconductor substrate, the second active surface of the second semiconductor substrate facing the first inactive surface of the first semiconductor substrate, and the plurality of second semiconductor chips being stacked on the first semiconductor chip;
• a plurality of first bonding pads between the first semiconductor chip and a lowermost second semiconductor chip of the plurality of second semiconductor chips, the plurality of first bonding pads electrically connecting the plurality of first through-electrodes of the first semiconductor chip to the plurality of second through-electrodes of the lowermost second semiconductor chip, the plurality of first bonding pads passing through the first backside insulation layer of the first semiconductor chip and the second front insulation layer of the lowermost second semiconductor chip of the plurality of second semiconductor chips;
• a plurality of second bonding pads between two second semiconductor chips of the plurality of second semiconductor chips, the two second semiconductor chips being adjacent to each other in a vertical direction, the plurality of second bonding pads electrically connecting the plurality of second through-electrodes of each of the plurality of second through-electrodes of the two second semiconductor chips, the plurality of second bonding pads passing through a second backside insulation layer of a lower second semiconductor chip and a second front insulation layer of an upper second semiconductor chip among the two second semiconductor chips adjacent to each other in the vertical direction;
• a dummy chip including a dummy substrate having a substrate top surface and a substrate bottom surface opposite to the substrate top surface, the substrate bottom surface of the dummy substrate facing an uppermost second semiconductor chip of the plurality of second semiconductor chips, and the dummy chip being attached to the plurality of second semiconductor chips;
• and
• a package molding layer on the first semiconductor chip, the package molding layer covering an upper surface of the first semiconductor chip, side surfaces of the plurality of second semiconductor chips, and a side surface of the dummy chip,
• wherein the dummy chip comprises a plurality of trenches receiving a filling molding portion of the package molding layer, the plurality of trenches extending into the dummy substrate from a side surface of the dummy chip and extending into the dummy substrate from a lower surface of the dummy chip.

A semiconductor package comprising:

• a first semiconductor chip including a first semiconductor substrate having a first active surface and a first inactive surface opposite to the first active surface, a plurality of first through-electrodes passing through the first semiconductor substrate, a plurality of package connection pads connected to the plurality of first through-electrodes on the first active surface of the first semiconductor substrate, a first front insulation layer surrounding the plurality of package connection pads on the first active surface of the first semiconductor substrate, and a first backside insulation layer covering the first inactive surface of the first semiconductor substrate;
• a plurality of second semiconductor chips, each second semiconductor chip of the plurality of second semiconductor chips includes a second semiconductor substrate having a second active surface and a second inactive surface opposite to the second active surface, a plurality of second through-electrodes passing through the second semiconductor substrate, a second front insulation layer on the second active surface of the second semiconductor substrate, and a second backside insulation layer covering the second inactive surface of the second semiconductor substrate, the second active surface of the second semiconductor substrate facing the first inactive surface of the first semiconductor substrate, and the plurality of second semiconductor chips being stacked on the first semiconductor chip;
• a plurality of first bonding pads between the first semiconductor chip and a lowermost second semiconductor chip of the plurality of second semiconductor chips, the plurality of first bonding pads electrically connecting the plurality of first through-electrodes of the first semiconductor chip to the plurality of second through-electrodes of the lowermost second semiconductor chip, the plurality of first bonding pads passing through the first backside insulation layer of the first semiconductor chip and the second front insulation layer of the lowermost second semiconductor chip of the plurality of second semiconductor chips;
• a plurality of second bonding pads between two second semiconductor chips of the plurality of second semiconductor chips, the two second semiconductor chips being adjacent to each other in a vertical direction, the plurality of second bonding pads electrically connecting the plurality of second through-electrodes of each of the plurality of second through-electrodes of the two second semiconductor chips, the plurality of second bonding pads passing through a second backside insulation layer of a lower second semiconductor chip and a second front insulation layer of an upper second semiconductor chip of the two second semiconductor chips adjacent to each other in the vertical direction;
• a dummy chip including a dummy substrate having a substrate top surface and a substrate bottom surface opposite to the substrate top surface and a bonding insulation layer covering the substrate bottom surface of the dummy substrate, the bonding insulation layer facing an uppermost second semiconductor chip of the plurality of second semiconductor chips and being attached to the plurality of second semiconductor chips;
• and
• a package molding layer on the first semiconductor chip, the package molding layer covering an upper surface of the first semiconductor chip, side surfaces of the plurality of second semiconductor chips, and a side surface of the dummy chip,
• wherein the dummy chip comprises a plurality of trenches receiving a filling molding portion of the package molding layer, the plurality of trenches extending from a first side surface of the dummy chip to a second side surface of the dummy chip, and passing through the substrate bottom surface of the dummy substrate from a lower surface of the bonding insulation layer and extending into the dummy substrate.