Semiconductor package and method of manufacturing the same

A semiconductor package, comprising:

• a substrate;
• a semiconductor device on an upper portion of the substrate and comprising at least one semiconductor chip;
• a plurality of bonding structures coupling the substrate with the semiconductor device;
• and
• an insulating structure on an upper surface of the substrate and at least partially surrounding the plurality of bonding structures,
• wherein each of the plurality of bonding structures comprises a connection via and a solder material layer,
• wherein the connection via extends vertically from a lower pad of the semiconductor device to an upper pad of the substrate,
• wherein an upper surface of the solder material layer is in contact with a lower surface of the lower pad of the semiconductor device,
• wherein a lower surface of the solder material layer is in contact with an upper surface of an upper pad of the substrate, and
• wherein an outer surface of the solder material layer is in contact with an inner surface of the connection via.

A semiconductor package, comprising:

• a plurality of semiconductor chips stacked in a vertical direction;
• and
• a plurality of bonding structures coupling two adjacent semiconductor chips from among the plurality of semiconductor chips, the two adjacent semiconductor chips comprising a lower-layer semiconductor chip and an upper-layer semiconductor chip;
• wherein each bonding structure of the plurality of bonding structures comprises a connection via and a solder material layer,
• wherein the solder material layer extends vertically from a lower surface of the upper-layer semiconductor chip to an upper pad of the lower-layer semiconductor chip, and
• wherein the connection via at least partially surrounds the solder material layer.