Semiconductor device and manufacturing method thereof

A method of manufacturing a semiconductor device, the method comprising:

• forming a recessed portion in a semi-finished product comprising a substrate, a source/drain area on the substrate, a first interlayer insulating film on the substrate, a contact plug penetrating at least a portion of the first interlayer insulating film along a first direction perpendicular to a surface of the substrate and electrically connected to the source/drain area and a second interlayer insulating film on the first interlayer insulating film, by etching the second interlayer insulating film along the first direction until the contact plug is exposed;
• forming a protecting film on at least an inner wall of the recessed portion;
• forming a wiring via to be electrically connected to the contact plug;
• and
• forming a wiring line to be electrically connected to the wiring via.

A semiconductor device comprising:

• a substrate;
• a source/drain area on the substrate;
• a first interlayer insulating film on the substrate;
• a contact plug penetrating at least a portion of the first interlayer insulating film along a first direction perpendicular to a surface of the substrate and electrically connected to the source/drain area;
• a second interlayer insulating film on the first interlayer insulating film;
• a wiring via penetrating a portion of the second interlayer insulating film along the first direction and electrically connected to the contact plug;
• a wiring line penetrating at least a portion of the second interlayer insulating film along the first direction and electrically connected to the wiring via;
• a protecting film between the wiring via and the second interlayer insulating film and between the wiring line and the second interlayer insulting film, and the protecting film comprising silicon oxide;
• a barrier film between the protecting film and the wiring line and surrounding at least a portion of the wiring via;
• a liner film between the barrier film and the wiring line and surrounding at least a portion of the wiring via;
• and
• an interlayer etching stopping film between the first interlayer insulating film and the second interlayer insulating film,
• the wiring via penetrating a portion of the first interlayer insulating film and the interlayer etching stopping film along the first direction,
• the wiring via comprising a first via area surrounded by the first interlayer insulating film and a second via area that is an area other than the first via area,
• the first via area comprising a via area 1-1 that is adjacent to the contact plug and a via area 1-2 that is an area other than the via area 1-1,
• the via area 1-1 having a grain size that is smaller than a grain size of the via area 1-2, and
• the grain size of the via area 1-1 being smaller than the grain size of the second via area.