Semiconductor package

A semiconductor package comprising:

• a first semiconductor chip;
• a molding layer surrounding the first semiconductor chip;
• a redistribution layer on an upper surface of the molding layer;
• a second semiconductor chip on the redistribution layer in a face-up form;
• and
• a third semiconductor chip on the second semiconductor chip in a face-down form,
• wherein the redistribution layer comprises:
• a first insulating pattern;
• a power delivery network (PDN) pattern in the first insulating pattern;
• and
• a redistribution pad exposed through an upper surface of the first insulating pattern,
• wherein the second semiconductor chip comprises:
• a first chip pad at a lower surface of the second semiconductor chip;
• and
• a second chip pad at an upper surface of the second semiconductor chip,
• wherein the third semiconductor chip comprises a third chip pad at a lower surface of the third semiconductor chip,
• wherein an upper surface of the redistribution layer and the lower surface of the second semiconductor chip are in contact with each other,
• wherein, at an interface of the redistribution layer and the second semiconductor chip, the redistribution pad and the first chip pad are composed of a same material as each other,
• wherein the upper surface of the second semiconductor chip and the lower surface of the third semiconductor chip are in contact with each other, and
• wherein the PDN pattern is electrically insulated from the first semiconductor chip, and is electrically connected to the second semiconductor chip.

A semiconductor package comprising:

• a first semiconductor chip;
• a molding layer surrounding the first semiconductor chip, and on an upper surface of the first semiconductor chip;
• a redistribution layer in contact with an upper surface of the molding layer;
• a conductive post beside the first semiconductor chip, the conductive post vertically penetrating the molding layer and connecting to the redistribution layer;
• a second semiconductor chip in contact with an upper surface of the redistribution layer;
• a third semiconductor chip on the second semiconductor chip, an active surface of the second semiconductor chip and an active surface of the third semiconductor chip being in contact with each other;
• and
• external terminals on a lower surface of the first semiconductor chip and a lower surface of the molding layer, and electrically connected to the conductive post and the first semiconductor chip,
• wherein a side surface of the molding layer, a side surface of the redistribution layer, a side surface of the second semiconductor chip, and a side surface of the third semiconductor chip are coplanar with each other,
• wherein the first semiconductor chip comprises a chip via penetrating the first semiconductor chip and the molding layer and connected to the redistribution layer, and
• wherein the redistribution layer comprises:
• a power delivery network (PDN) pattern electrically connected to the second semiconductor chip, and electrically insulated from the first semiconductor chip;
• and
• a wiring pattern connected to the chip via.