Semiconductor package and manufacturing method thereof

A semiconductor package comprising

• a first semiconductor chip comprising:
• a first normal region overlapping in a plane a center of a first surface of a first substrate,
• a plurality of signal power pads,
• a first test region overlapping edges of the first surface,
• a plurality of first dummy pads electrically connected to each other,
• a plurality of second dummy pads positioned adjacent to the plurality of first dummy pads, wherein each second dummy pad of the plurality of second dummy pads is floated, and
• a first alignment key positioned adjacent to the plurality of first dummy pads and the plurality of second dummy pads;
• and
• a second semiconductor chip comprising:
• a second test region overlapping the first test region with at least a portion on a second surface of a second substrate facing the first surface of the first substrate,
• a plurality of power pads having at least a part that overlaps the plurality of second dummy pads and configured to provide a test voltage, and
• a second alignment key corresponding to the first alignment key.

A manufacturing method of a semiconductor package comprising:

• bonding a first semiconductor chip onto a first surface of a second semiconductor chip at a wafer level using an alignment key;
• providing a test signal to the second semiconductor chip using a test pad arranged on a second surface of the second semiconductor chip opposite to the first surface of the second semiconductor chip;
• testing an alignment of a stacking structure including the first semiconductor chip and the second semiconductor chip by detecting a current corresponding to the test signal at the test pad;
• and
• sawing a wafer including the second semiconductor chip.