Non-oxide dielectric spacers for resistive random-access memory

An integrated circuit device, comprising:

• a metal interconnect structure disposed over a semiconductor substrate, wherein the metal interconnect structure includes a plurality of metallization layers separated by via layers, each metallization layer comprising conductive traces surrounded by an inter-layer dielectric (ILD), and each via layer comprising conductive vias that interconnect the conductive traces and are surrounded by the inter-layer dielectric;
• an RRAM (Resistive Random Access Memory) cell comprising a bottom electrode, a top electrode, and a resistive switching structure located between the bottom electrode and the top electrode, wherein the RRAM cell is integrated within the metal interconnect structure, and an upper surface of the top electrode includes a tapered recess;
• a first spacer disposed on an upper surface of the resistive switching structure and along outer sidewalls of the top electrode;
• and
• a second dielectric layer surrounding the bottom electrode, wherein the second dielectric layer provides a physical barrier between the bottom electrode and the inter-layer dielectric and is of a type that may be formed in an oxygen-free deposition process.

A method of manufacturing an integrated circuit device, the method comprising:

• forming a metallization layer over a surface of the semiconductor substrate, wherein the metallization layer comprises a conductive trace;
• depositing a dielectric layer over the metallization layer;
• forming a hole through the dielectric layer, wherein the conductive trace is exposed through the hole;
• depositing a bottom electrode layer, a resistive switching structure, and a top electrode layer over the dielectric layer and the hole, wherein each of the bottom electrode layer, the resistive switching structure, and the top electrode layer have central depressions over the hole;
• forming a hard mask over the top electrode layer;
• performing a first etch process to etch through the top electrode layer and define a top electrode;
• forming a sidewall spacer around the top electrode;
• using a second etch process to etch through the bottom electrode layer to define a bottom electrode and expose a bottom electrode sidewall, wherein either the first etch process or the second etch process etches through the resistive switching structure to define a resistive switching structure, and the bottom electrode, the top electrode, and the resistive switching structure together provide a resistive random-access memory (RRAM) cell;
• depositing a non-oxide dielectric layer over the bottom electrode sidewall using a substantially oxygen-free deposition process;
• and
• depositing an inter-layer dielectric (ILD), wherein the non-oxide dielectric layer protects the bottom electrode from oxidation during the deposition of the ILD.